公开(公告)号：US20240096805A1

公开(公告)日：2024-03-21

申请号：US18526445

申请日：2023-12-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

摘要： In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US11862561B2

公开(公告)日：2024-01-02

申请号：US17126509

申请日：2020-12-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/00

CPC分类号： H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

摘要： In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US11581300B2

公开(公告)日：2023-02-14

申请号：US17092100

申请日：2020-11-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Charles Chew-Yuen Young ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Shun-Li Chen ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Chun-Kuang Chen ,  Ru-Gun Liu

IPC分类号： H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528 ,  H01L29/66 ,  H01L21/84

摘要： A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US11328957B2

公开(公告)日：2022-05-10

申请号：US16800834

申请日：2020-02-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

摘要： A device includes a first transistor, a second transistor, and a contact. The first transistor includes a first source/drain, a second source/drain, and a first gate between the first and second source/drains. The second transistor includes a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains. The contact covers the first source/drain of the first transistor and the third source/drain of the second transistor. The contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the second transistor.

公开(公告)号：US11024579B2

公开(公告)日：2021-06-01

申请号：US16382478

申请日：2019-04-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02

摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.

公开(公告)号：US20210028311A1

公开(公告)日：2021-01-28

申请号：US17068444

申请日：2020-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Lei-Chun Chou

IPC分类号： H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48

摘要： The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US10861790B2

公开(公告)日：2020-12-08

申请号：US16216075

申请日：2018-12-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Pin-Dai Sue ,  Ru-Gun Liu ,  Shih-Wei Peng ,  Wen-Hao Chen ,  Yung-Sung Yen ,  Chun-Kuang Chen

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L21/768

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.

公开(公告)号：US20180174967A1

公开(公告)日：2018-06-21

申请号：US15898882

申请日：2018-02-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Pin-Dai Sue ,  Ru-Gun Liu ,  Shih-Wei Peng ,  Wen-Hao Chen ,  Yung-Sung Yen ,  Chun-Kuang Chen

IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L23/5286 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211

摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and middle-end-of-the-line (MEOL) structures extending in a first direction over an active area of a substrate. The MEOL structures are interleaved between the gate structures along a second direction. The method further forms a power rail and a first metal wire extending in the second direction. The first metal wire is over the MEOL structures. A double patterning process is performed to form second and third metal wires extending in the first direction over the first metal wire and separated in the second direction. The second metal wire is cut according to a first cut region of a first cut mask to define a first metal strap connecting a first one of the MEOL structures to the power rail.

公开(公告)号：US11862623B2

公开(公告)日：2024-01-02

申请号：US18167651

申请日：2023-02-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Charles Chew-Yuen Young ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Shun-Li Chen ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Chun-Kuang Chen ,  Ru-Gun Liu

IPC分类号： H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528 ,  H01L29/66 ,  H01L21/84

CPC分类号： H01L27/0207 ,  G06F30/394 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/528 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US20230387035A1

公开(公告)日：2023-11-30

申请号：US18232713

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kam-Tou SIO ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-Cheng Lin

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/5389 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4857 ,  H01L24/20 ,  H01L2224/214

摘要： The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.