公开(公告)号：US12080588B2

公开(公告)日：2024-09-03

申请号：US18358321

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC分类号： H01L21/74 ,  H01L23/535 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/762 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/66795 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/785 ,  H10B10/12

摘要： A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US20240096805A1

公开(公告)日：2024-03-21

申请号：US18526445

申请日：2023-12-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

摘要： In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US11862561B2

公开(公告)日：2024-01-02

申请号：US17126509

申请日：2020-12-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/00

CPC分类号： H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

摘要： In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US20230377941A1

公开(公告)日：2023-11-23

申请号：US18358321

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC分类号： H01L21/74 ,  H01L23/535 ,  H01L29/66

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/66795 ,  H01L21/3081

摘要： A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US11581300B2

公开(公告)日：2023-02-14

申请号：US17092100

申请日：2020-11-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Charles Chew-Yuen Young ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Shun-Li Chen ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Chun-Kuang Chen ,  Ru-Gun Liu

IPC分类号： H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528 ,  H01L29/66 ,  H01L21/84

摘要： A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

公开(公告)号：US11515308B2

公开(公告)日：2022-11-29

申请号：US16900768

申请日：2020-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/092 ,  G06F30/392

摘要： An IC structure includes first and second cell rows extending in a first direction. The first cell row includes first cells each including one or more first fins having first source/drain regions of a first conductivity type and one or more second fins having second source/drain regions of a second conductivity type opposite the first conductivity type. The second cell row includes second cells each including one or more third fins having third source/drain regions of the first conductivity type and one or more fourth fins having fourth source/drain regions of the second conductivity type. The first cells have a same first number of the one or more first fins, and the second cells have a same second number of the one or more third fins less than the first number of the one or more first fins.

公开(公告)号：US11495687B2

公开(公告)日：2022-11-08

申请号：US17001390

申请日：2020-08-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L21/74 ,  H01L23/538 ,  H01L23/535 ,  H01L29/417

摘要： The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US11328957B2

公开(公告)日：2022-05-10

申请号：US16800834

申请日：2020-02-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

摘要： A device includes a first transistor, a second transistor, and a contact. The first transistor includes a first source/drain, a second source/drain, and a first gate between the first and second source/drains. The second transistor includes a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains. The contact covers the first source/drain of the first transistor and the third source/drain of the second transistor. The contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the second transistor.

公开(公告)号：US11309311B2

公开(公告)日：2022-04-19

申请号：US16787964

申请日：2020-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Po-Chia Lai ,  Shang-Wei Fang ,  Meng-Hung Shen ,  Jiann-Tyng Tzeng ,  Ting-Wei Chiang ,  Jung-Chan Yang ,  Stefan Rusu

IPC分类号： H01L21/44 ,  H01L29/40 ,  H01L27/07 ,  H01L27/02 ,  H01L23/485 ,  G06F30/392 ,  H01L23/64 ,  G06F30/394

摘要： An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.

公开(公告)号：US20210280607A1

公开(公告)日：2021-09-09

申请号：US17328534

申请日：2021-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang CHEN ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Chia-Tien Wu ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wei-Cheng Lin ,  Lei-Chun Chou ,  Wei-An Lai

IPC分类号： H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/02

摘要： The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.