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公开(公告)号：US11862623B2
公开(公告)日：2024-01-02
申请号：US18167651
申请日：2023-02-10
发明人： Charles Chew-Yuen Young , Chih-Liang Chen , Chih-Ming Lai , Jiann-Tyng Tzeng , Shun-Li Chen , Kam-Tou Sio , Shih-Wei Peng , Chun-Kuang Chen , Ru-Gun Liu
IPC分类号： H01L27/02 , H01L21/768 , H01L21/8234 , H01L23/485 , G06F30/394 , H01L23/528 , H01L29/66 , H01L21/84
CPC分类号： H01L27/0207 , G06F30/394 , H01L21/76895 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L23/485 , H01L21/76897 , H01L21/845 , H01L23/528 , H01L29/6656 , H01L29/6659 , H01L2924/0002 , H01L2924/0002 , H01L2924/00
摘要： A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
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公开(公告)号：US11063005B2
公开(公告)日：2021-07-13
申请号：US16682377
申请日：2019-11-13
发明人： Kam-Tou Sio , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Ru-Gun Liu , Wen-Hao Chen
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522 , H01L23/485 , H01L21/8234 , H01L23/532
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.
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公开(公告)号：US11024623B2
公开(公告)日：2021-06-01
申请号：US16933127
申请日：2020-07-20
发明人： Hung-Wen Cho , Fu-Jye Liang , Chun-Kuang Chen , Chih-Tsung Shih , Li-Jui Chen , Po-Chung Cheng , Chin-Hsiang Lin
摘要： A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.
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公开(公告)号：US10833061B2
公开(公告)日：2020-11-10
申请号：US16216843
申请日：2018-12-11
发明人： Charles Chew-Yuen Young , Chih-Liang Chen , Chih-Ming Lai , Jiann-Tyng Tzeng , Shun-Li Chen , Kam-Tou Sio , Shih-Wei Peng , Chun-Kuang Chen , Ru-Gun Liu
IPC分类号： H01L21/768 , H01L23/528 , H01L27/02 , H01L21/8234 , H01L23/485 , G06F30/394 , H01L29/66 , H01L21/84
摘要： Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.
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公开(公告)号：US10784168B2
公开(公告)日：2020-09-22
申请号：US16154035
申请日：2018-10-08
发明人： Hui-Ting Yang , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Meng-Hung Shen , Ru-Gun Liu , Wei-Cheng Lin
IPC分类号： H01L27/02 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78 , H01L29/49 , H01L21/8234 , H01L29/66
摘要： The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.
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公开(公告)号：US20190122987A1
公开(公告)日：2019-04-25
申请号：US16216075
申请日：2018-12-11
发明人： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Kam-Tou Sio , Pin-Dai Sue , Ru-Gun Liu , Shih-Wei Peng , Wen-Hao Chen , Yung-Sung Yen , Chun-Kuang Chen
IPC分类号： H01L23/528 , H01L27/12 , H01L27/088 , H01L21/84 , H01L21/8234 , H01L27/092 , H01L23/522 , H01L21/8238
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.
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公开(公告)号：US10203606B1
公开(公告)日：2019-02-12
申请号：US15873944
申请日：2018-01-18
摘要： A dispensing head for dispensing a developer onto a substrate is provided. The dispensing head includes a housing configured to receive the developer. The dispensing head further includes at least one liquid outlet provided on the housing. The liquid outlet is configured to spray the developer onto an elongated area on the substrate. Also, the liquid outlet is configured to spray the developer along a dispensing direction that is tilted with respect to the normal direction of the substrate and perpendicular to the long-axis direction of the elongated area.
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公开(公告)号：US10114291B2
公开(公告)日：2018-10-30
申请号：US15061364
申请日：2016-03-04
发明人： Ya-Ling Cheng , Ching-Yu Chang , Chien-Chih Chen , Chun-Kuang Chen , Siao-Shan Wang , Wei-Liang Lin
IPC分类号： H01L21/31 , G03F7/32 , H01L21/02 , H01L21/027 , H01L21/308 , G03F7/004 , G03F7/40 , G03F7/42
摘要： A method includes forming a first layer over a substrate; forming a patterned photoresist layer over the first layer; applying a solution over the patterned photoresist layer to form a conformal layer over the pattern photoresist layer, wherein the conformal layer further includes a first portion over a top surface of the patterned photoresist layer and second portion extending along sidewalls of the patterned photoresist layer; selectively removing the first portion of the conformal layer formed over the top surface of the patterned photoresist layer; and selectively removing the patterned photoresist layer thereby leaving the second portion of the conformal layer.
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公开(公告)号：US09793211B2
公开(公告)日：2017-10-17
申请号：US15213486
申请日：2016-07-19
发明人： Shih-Wei Peng , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Yung-Sung Yen
IPC分类号： H01L23/538 , H01L23/528 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5286 , H01L21/76816 , H01L21/76892 , H01L23/5226 , H01L23/528 , H01L28/00
摘要： The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues.
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公开(公告)号：US09754881B2
公开(公告)日：2017-09-05
申请号：US15050087
申请日：2016-02-22
发明人： Chih-Liang Chen , Chih-Ming Lai , Yung-Sung Yen , Kam-Tou Sio , Tsong-Hua Ou , Chun-Kuang Chen , Ru-Gun Liu , Shu-Hui Sung , Charles Chew-Yuen Young
IPC分类号： H01L27/118 , H01L23/528 , H01L23/522 , H01L27/02
CPC分类号： H01L23/528 , H01L23/5226 , H01L27/0207 , H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 P gate min + 0.35 L gate min + 0.3 H gate min - 20 0.2 L gate min + 0.8 H gate min - 5 × 0.3 L gate min + 0.3 H gate min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.
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