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公开(公告)号：US11854807B2
公开(公告)日：2023-12-26
申请号：US16806206
申请日：2020-03-02
发明人： Chih-Min Hsiao , Chien-Wen Lai , Ru-Gun Liu , Chih-Ming Lai , Shih-Ming Chang , Yung-Sung Yen , Yu-Chen Chang
IPC分类号： H01L21/033 , H01L21/3115 , H01L21/311 , H01L21/265
CPC分类号： H01L21/0338 , H01L21/0335 , H01L21/0337 , H01L21/26586 , H01L21/31116 , H01L21/31144 , H01L21/31155
摘要： Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.
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公开(公告)号：US20230384691A1
公开(公告)日：2023-11-30
申请号：US18361879
申请日：2023-07-30
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705
摘要： A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.
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公开(公告)号：US20220223474A1
公开(公告)日：2022-07-14
申请号：US17705487
申请日：2022-03-28
发明人： Ru-Gun Liu , Shih-Ming Chang , Hoi-Tou Ng
IPC分类号： H01L21/768 , H01L21/311 , H01L21/027 , H01L23/522
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first conductive feature embedded in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. The first conductive feature includes a metal layer and a reflective layer on the metal layer. The reflective layer has a reflectivity higher than the metal layer.
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公开(公告)号：US11294286B2
公开(公告)日：2022-04-05
申请号：US16287450
申请日：2019-02-27
发明人： Ru-Gun Liu , Chin-Hsiang Lin , Cheng-I Huang , Chih-Ming Lai , Chien-Wen Lai , Ken-Hsien Hsieh , Shih-Ming Chang , Yuan-Te Hou
摘要： A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
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公开(公告)号：US11289376B2
公开(公告)日：2022-03-29
申请号：US16892984
申请日：2020-06-04
发明人： Ru-Gun Liu , Shih-Ming Chang , Hoi-Tou Ng
IPC分类号： H01L21/768 , H01L21/311 , H01L21/027 , H01L23/522
摘要： The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.
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公开(公告)号：US11054748B2
公开(公告)日：2021-07-06
申请号：US16138402
申请日：2018-09-21
发明人： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
摘要： An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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公开(公告)号：US10698320B2
公开(公告)日：2020-06-30
申请号：US15427496
申请日：2017-02-08
发明人： Ru-Gun Liu , Shih-Ming Chang , Shuo-Yen Chou , Zengqin Zhao , Chien Wen Lai
IPC分类号： G03F7/20 , G03F9/00 , H01L23/544
摘要： A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.
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公开(公告)号：US20200098545A1
公开(公告)日：2020-03-26
申请号：US16138402
申请日：2018-09-21
发明人： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
IPC分类号： H01J37/317 , H01J37/302 , G03F7/20 , G03F1/78
摘要： An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
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公开(公告)号：US10514613B2
公开(公告)日：2019-12-24
申请号：US15398839
申请日：2017-01-05
发明人： Shih-Ming Chang , Ru-Gun Liu , Shuo-Yen Chou , Chien-Wen Lai , Zengqin Zhao
摘要： A pattern modification method and a patterning process are provided. The method includes extracting a first pattern and a second pattern to be respectively transferred to a first target portion and a second target portion of a resist layer. The method also includes obtaining regional information of the first target portion and the second target portion. The method includes determining a first desired focus position for transferring the first pattern based on the regional information. In addition, the method includes determining a second desired focus position for transferring the second pattern based on the regional information. The method includes modifying one or both of the first pattern and the second pattern. As a result, focus positions of the first pattern and the second pattern are shifted to be substantially and respectively positioned at the first desired focus position and the second desired focus position during an exposure operation.
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公开(公告)号：US20180165388A1
公开(公告)日：2018-06-14
申请号：US15427496
申请日：2017-02-08
发明人： Ru-Gun Liu , Shih-Ming Chang , Shuo-Yen Chou , Zengqin Zhao , Chien Wen Lai
IPC分类号： G06F17/50
摘要： A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.
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