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公开(公告)号：US11782352B2
公开(公告)日：2023-10-10
申请号：US17815155
申请日：2022-07-26
发明人： Chih-Jie Lee , Shih-Chun Huang , Shih-Ming Chang , Ken-Hsien Hsieh , Yung-Sung Yen , Ru-Gun Liu
CPC分类号： G03F9/7026 , G03F7/2004 , G03F7/2041
摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
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公开(公告)号：US11543753B2
公开(公告)日：2023-01-03
申请号：US16886509
申请日：2020-05-28
发明人： Ken-Hsien Hsieh , Shih-Ming Chang , Wen Lo , Wei-Shuo Su , Hua-Tai Lin
IPC分类号： G03F7/20
摘要： In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.
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公开(公告)号：US20220155692A1
公开(公告)日：2022-05-19
申请号：US17665757
申请日：2022-02-07
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
摘要： A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.
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公开(公告)号：US11243472B2
公开(公告)日：2022-02-08
申请号：US16895547
申请日：2020-06-08
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
摘要： A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.
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公开(公告)号：US10962892B2
公开(公告)日：2021-03-30
申请号：US16227939
申请日：2018-12-20
发明人： Chih-Jie Lee , Shih-Chun Huang , Shih-Ming Chang , Ken-Hsien Hsieh , Yung-Sung Yen , Ru-Gun Liu
摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
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公开(公告)号：US10678142B2
公开(公告)日：2020-06-09
申请号：US16057277
申请日：2018-08-07
发明人： Dong-Yo Jheng , Ken-Hsien Hsieh , Shih-Ming Chang , Chih-Jie Lee , Shuo-Yen Chou , Ru-Gun Liu
摘要： Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.
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公开(公告)号：US20190080921A1
公开(公告)日：2019-03-14
申请号：US15704367
申请日：2017-09-14
发明人： Ken-Hsien Hsieh , Wen-Li Cheng , Dong-Yo Jheng , Chih-Ming Lai , Ru-Gun Liu
IPC分类号： H01L21/308 , G06F17/50
摘要： A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.
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公开(公告)号：US20190042685A1
公开(公告)日：2019-02-07
申请号：US16133110
申请日：2018-09-17
发明人： Ken-Hsien Hsieh , Chih-Ming Lai , Ru-Gun Liu , Wen-Chun Huang , Wen-Li Cheng , Pai-Wei Wang
摘要： Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.
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公开(公告)号：US20170338115A1
公开(公告)日：2017-11-23
申请号：US15593214
申请日：2017-05-11
发明人： Yung-Sung Yen , Ken-Hsien Hsieh , Ru-Gun Liu
IPC分类号： H01L21/033 , H01L21/768 , H01L23/528
CPC分类号： H01L21/76816 , H01L21/0273 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76802 , H01L23/528 , H01L23/5283
摘要： Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.
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公开(公告)号：US12085867B2
公开(公告)日：2024-09-10
申请号：US18360618
申请日：2023-07-27
发明人： Chih-Jie Lee , Shih-Chun Huang , Shih-Ming Chang , Ken-Hsien Hsieh , Yung-Sung Yen , Ru-Gun Liu
CPC分类号： G03F9/7026 , G03F7/2004 , G03F7/2041
摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
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