-
公开(公告)号：US20190067264A1
公开(公告)日：2019-02-28
申请号：US15904959
申请日：2018-02-26
发明人： Hidehiro FUJIWARA , Hung-Jen LIAO , Hsien-Yu PAN , Chih-Yu LIN , Yen-Huei CHEN , Sahil Preet SINGH
摘要： A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.
-
公开(公告)号：US20180130809A1
公开(公告)日：2018-05-10
申请号：US15864873
申请日：2018-01-08
IPC分类号： H01L27/11 , H01L23/528 , G11C11/412 , G11C11/419 , H01L23/532 , H01L23/522
CPC分类号： H01L27/1112 , G11C5/025 , G11C5/14 , G11C11/412 , G11C11/419 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L23/53209 , H01L23/53257 , H01L28/00
摘要： A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell; causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.
-
公开(公告)号：US20160111143A1
公开(公告)日：2016-04-21
申请号：US14515253
申请日：2014-10-15
发明人： Chih-Yu LIN , Wei-Cheng WU , Kao-Cheng LIN , Yen-Huei CHEN
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM.
摘要翻译： 包括至少第一存储单元阵列，第二存储单元阵列，连接到第一存储单元阵列和第二存储单元阵列的第一数据线的静态随机存取存储器（SRAM），连接到第一数据的主驱动器电路 线路和连接到第一数据线路的辅助驱动器电路，其中辅助驱动器电路被配置为在SRAM的写入操作期间将第一数据线的电压电平拉到第一电压电平。
-
公开(公告)号：US20150348598A1
公开(公告)日：2015-12-03
申请号：US14291443
申请日：2014-05-30
发明人： Li-Wen WANG , Chih-Yu LIN , Yen-Huei CHEN , Hung-Jen LIAO
IPC分类号： G11C5/10 , G11C11/417
CPC分类号： G11C11/417 , G11C11/419
摘要： A static random access memory (SRAM) that includes a memory cell comprising at least two p-type pass gates. The SRAM also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control the memory cell.
摘要翻译： 一种静态随机存取存储器（SRAM），其包括包含至少两个p型通过门的存储单元。 SRAM还包括连接到存储单元的第一数据线，连接到存储单元的第二数据线和连接到第一数据线的电压控制单元，其中电压控制单元被配置为控制存储单元。
-
公开(公告)号：US20240357788A1
公开(公告)日：2024-10-24
申请号：US18756363
申请日：2024-06-27
发明人： Hidehiro FUJIWARA , Chih-Yu LIN , Hsien-Yu PAN , Yasutoshi OKUNO , Yen-Huei CHEN , Hung-Jen LIAO
IPC分类号： H10B10/00 , G06F30/392 , H01L23/522 , H01L23/528 , H01L27/02
CPC分类号： H10B10/12 , G06F30/392 , H01L23/5226 , H01L23/5286 , H01L27/0207
摘要： A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.
-
公开(公告)号：US20230238056A1
公开(公告)日：2023-07-27
申请号：US17585824
申请日：2022-01-27
发明人： Yi-Hsin NIEN , Hidehiro FUJIWARA , Chih-Yu LIN , Yen-Huei CHEN
IPC分类号： G11C11/412 , H01L27/11 , G11C11/419
CPC分类号： G11C11/412 , H01L27/1104 , G11C11/419
摘要： A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.
-
公开(公告)号：US20220093172A1
公开(公告)日：2022-03-24
申请号：US17541240
申请日：2021-12-02
发明人： Chih-Yu LIN , Wei-Cheng WU , Kao-Cheng LIN , Yen-Huei CHEN
IPC分类号： G11C11/419
摘要： A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of a first memory cell in the first memory cell array in response to at least a first NOR output signal.
-
公开(公告)号：US20210408011A1
公开(公告)日：2021-12-30
申请号：US17225627
申请日：2021-04-08
发明人： Hidehiro FUJIWARA , Chih-Yu LIN , Yen-Huei CHEN , Wei-Chang ZHAO , Yi-Hsin NIEN
IPC分类号： H01L27/11 , H01L23/522 , H01L23/528 , G06F30/392
摘要： A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second reference voltage.
-
公开(公告)号：US20210217742A1
公开(公告)日：2021-07-15
申请号：US17213074
申请日：2021-03-25
发明人： Hidehiro FUJIWARA , Sahil Preet SINGH , Chih-Yu LIN , Hsien-Yu PAN , Yen-Huei CHEN , Hung-Jen LIAO
IPC分类号： H01L27/02 , H01L27/11 , H01L23/522 , G11C5/06 , G11C7/18
摘要： A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.
-
公开(公告)号：US20170207227A1
公开(公告)日：2017-07-20
申请号：US14995403
申请日：2016-01-14
IPC分类号： H01L27/11 , G11C11/419 , H01L23/532 , G11C11/412 , H01L23/528 , H01L23/522
CPC分类号： H01L27/1112 , G11C5/025 , G11C5/14 , G11C11/412 , G11C11/419 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L23/53209 , H01L23/53257 , H01L28/00
摘要： A memory circuit includes a first column of memory cells arranged along a first direction, a first supply voltage line extending along the first direction in a first conductive layer of the memory circuit, a second supply voltage line, a first resistive device electrically connecting the first supply voltage line and the second supply voltage line, and a supply voltage source. Each memory cell of the first column of memory cells includes a supply voltage line segment. The first supply voltage line is made of at least the supply voltage line segments of the first column of memory cells. The supply voltage source is electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device is in a lowest resistance path of the one or more conductive paths.
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.023 秒)
