公开(公告)号：US20190067264A1

公开(公告)日：2019-02-28

申请号：US15904959

申请日：2018-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Hsien-Yu PAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Sahil Preet SINGH

IPC分类号： H01L27/02 ,  H01L27/11

摘要： A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.

公开(公告)号：US20230245694A1

公开(公告)日：2023-08-03

申请号：US17744428

申请日：2022-05-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Atul KATOCH ,  Sahil Preet SINGH

IPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4099

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4099

摘要： A memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a sense amplifier, a driver circuit and a booster circuit. The sense amplifier is configured to sense a first signal in response to at least a sense amplifier signal. The first signal corresponds to a value of the data stored in the set of memory cells. The driver circuit is configured to generate a global bit line signal in response to at least the first signal or an inverted first signal. The booster circuit is coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal.

公开(公告)号：US20240363616A1

公开(公告)日：2024-10-31

申请号：US18769004

申请日：2024-07-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Sahil Preet SINGH ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H01L27/02 ,  G11C5/06 ,  G11C7/18 ,  H01L23/522 ,  H10B10/00

CPC分类号： H01L27/0207 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H10B10/12

摘要： A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

公开(公告)号：US20210217742A1

公开(公告)日：2021-07-15

申请号：US17213074

申请日：2021-03-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Sahil Preet SINGH ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L23/522 ,  G11C5/06 ,  G11C7/18

摘要： A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.