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公开(公告)号：US11977335B2
公开(公告)日：2024-05-07
申请号：US17353582
申请日：2021-06-21
Applicant: United Microelectronics Corp.
Inventor： Min Cheng Yang , Wei Cyuan Lo , Yung-Feng Cheng
CPC classification number: G03F7/70466 , G03F1/36 , G03F1/70 , G03F7/70475
Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.
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公开(公告)号：US20220157933A1
公开(公告)日：2022-05-19
申请号：US17118630
申请日：2020-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Heng Liu , Chia-Wei Huang , Hsin-Jen Yu , Yung-Feng Cheng , Ming-Jui Chen
IPC: H01L29/06 , H01L29/78 , H01L21/762 , H01L29/66
Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.
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公开(公告)号：US10444622B2
公开(公告)日：2019-10-15
申请号：US15892935
申请日：2018-02-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tsung-Yeh Wu , Chia-Wei Huang , Yung-Feng Cheng
Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
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公开(公告)号：US20180143529A1
公开(公告)日：2018-05-24
申请号：US15361007
申请日：2016-11-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-I Wei , Chia-Wei Huang , Yung-Feng Cheng
CPC classification number: G03F1/36 , G03F1/84 , G06F17/5081
Abstract: A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.
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公开(公告)号：US08782569B1
公开(公告)日：2014-07-15
申请号：US13802868
申请日：2013-03-14
Applicant: United Microelectronics Corp.
Inventor： Chain-Ting Huang , Yung-Feng Cheng , Ming-Jui Chen
IPC: G06F17/50
CPC classification number: G03F1/84
Abstract: An inspection method for a photo-mask in a semiconductor process is provided. First, a first photo-mask with a first wafer anchor point (1st wafer FAM) is provided. Then, Dmax and Dmin are calculated according to the 1st wafer FAM. A second photo-mask and a second mask anchor point (2nd mask FAM) of the second photo-mask are provided. A CD average, and a CD range of the second photo-mask are measured. Finally, the second photo-mask is inspected by using equation A and/or equation B: CD average−2nd mask FAM
Abstract translation: 提供了半导体工艺中的光掩模检查方法。 首先，提供具有第一晶片固定点（第一晶片FAM）的第一光掩模。 然后，根据第一晶片FAM计算Dmax和Dmin。 提供第二光掩模的第二光掩模和第二掩模锚定点（第二掩模FAM）。 测量CD平均值和第二光掩模的CD范围。 最后，使用等式A和/或等式B检查第二光掩模：CD平均第二掩模FAM
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公开(公告)号：US11715759B2
公开(公告)日：2023-08-01
申请号：US17118630
申请日：2020-12-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chien-Heng Liu , Chia-Wei Huang , Hsin-Jen Yu , Yung-Feng Cheng , Ming-Jui Chen
IPC: H01L29/06 , H01L29/66 , H01L29/78 , H01L21/762
CPC classification number: H01L29/0649 , H01L21/76224 , H01L29/66795 , H01L29/7851
Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.
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公开(公告)号：US20200212052A1
公开(公告)日：2020-07-02
申请号：US16234441
申请日：2018-12-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Chang Lin , Wei-Cyuan Lo , Yung-Feng Cheng
IPC: H01L27/11
Abstract: The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.
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公开(公告)号：US09859170B2
公开(公告)日：2018-01-02
申请号：US15434067
申请日：2017-02-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC: H01L21/8238 , H01L21/768 , H01L27/11 , H01L23/535 , H01L27/092 , H01L29/78
CPC classification number: H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.
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公开(公告)号：US11934106B2
公开(公告)日：2024-03-19
申请号：US17880700
申请日：2022-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shu-Yen Liu , Hui-Fang Kuo , Chian-Ting Huang , Wei-Cyuan Lo , Yung-Feng Cheng , Chung-Yi Chiu
CPC classification number: G03F7/70441 , G03F1/36 , G03F7/705
Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
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公开(公告)号：US20240005475A1
公开(公告)日：2024-01-04
申请号：US17878896
申请日：2022-08-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Pai-Chi Chen , Chian-Ting Huang , Yung-Feng Cheng
CPC classification number: G06T7/0006 , G06T7/62 , G06T2207/30148
Abstract: The present invention provides a photomask inspection method, including steps of defining an anchor ratio, providing a photomask and measuring the photomask to obtain a measured ratio, wherein the measured ratio is equal to a value of an image intensity extremum divided by an image intensity threshold or is equal to a value of the image intensity threshold divided by the image intensity extremum when the photomask is measured in an image measurement system tool for a specific critical dimension, and if the measured ratio is larger than the anchor ratio, the photomask is regarded as passing the inspection, and if the measured ratio is smaller than the anchor ratio, the photomask is regarded as failing the inspection.
