公开(公告)号：US12069873B2

公开(公告)日：2024-08-20

申请号：US17462040

申请日：2021-08-31

申请人： eMemory Technology Inc.

发明人： Tsung-Mu Lai ,  Wei-Chen Chang

IPC分类号： H10B99/00 ,  G11C11/416

CPC分类号： H10B99/00 ,  G11C11/416

摘要： A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.

公开(公告)号：US20170236824A1

公开(公告)日：2017-08-17

申请号：US15581646

申请日：2017-04-28

申请人： International Business Machines Corporation

发明人： Tak H. Ning

IPC分类号： H01L27/102 ,  H01L21/8229 ,  H01L21/8228 ,  G11C11/416 ,  G11C11/411

CPC分类号： G11C11/416 ,  G11C11/411 ,  G11C11/4116 ,  H01L21/8228 ,  H01L21/8229 ,  H01L27/1025 ,  H01L27/11

摘要： A method of forming a complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.

公开(公告)号：US09721050B2

公开(公告)日：2017-08-01

申请号：US15155236

申请日：2016-05-16

申请人： International Business Machines Corporation

发明人： Alexander Fritsch ,  Amira Rozenfeld ,  Rolf Sautter ,  Dieter Wendel

IPC分类号： G11C11/00 ,  G06F17/50 ,  G11C11/419 ,  G11C11/418 ,  H01L23/528 ,  H01L27/11 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18

CPC分类号： G11C11/416 ,  G06F17/5045 ,  G06F17/5081 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/418 ,  G11C11/419 ,  H01L23/528 ,  H01L27/1104

摘要： A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

公开(公告)号：US09496020B2

公开(公告)日：2016-11-15

申请号：US14740186

申请日：2015-06-15

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： G11C11/39 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  G11C11/411 ,  G11C11/416

CPC分类号： G11C11/39 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104

摘要： A memory cell based upon cross-coupled thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors with the thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells.

摘要翻译： 基于用于SRAM集成电路的交叉耦合晶闸管的存储单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合来实现。 标准CMOS工艺技术可用于制造SRAM单元。

公开(公告)号：US20160284406A1

公开(公告)日：2016-09-29

申请号：US14668896

申请日：2015-03-25

申请人： Intel Corporation

发明人： Shigeki Tomishima ,  Dmitri E. Nikonov ,  Elijah V. Ilya Karpov ,  Ian A. Young ,  Robert S. Chau

IPC分类号： G11C14/00 ,  G11C13/00

CPC分类号： G11C14/009 ,  G11C11/4116 ,  G11C11/412 ,  G11C11/413 ,  G11C11/416 ,  G11C11/419 ,  G11C13/0097

摘要： An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a SRAM cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two NV resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell.

摘要翻译： 提供了一种装置，其包括：具有集成在该SRAM单元内的至少两个非易失性（NV）电阻存储器元件的静态随机存取存储器（SRAM）单元; 以及将存储在SRAM单元中的数据自存储到至少两个NV电阻存储器元件的第一逻辑。 提供了一种方法，其包括当施加到SRAM单元的电压降低到阈值电压时执行自存储操作，以将SRAM单元的电压状态存储到至少两个NV电阻存储器元件，其中至少两个NV 电阻存储元件与SRAM单元集成; 以及当通过将来自所述至少两个NV电阻性存储器元件的数据复制到所述SRAM单元的存储节点的情况下，施加到所述SRAM单元的电压增加到阈值电压时，执行自恢复操作。

公开(公告)号：US09336860B1

公开(公告)日：2016-05-10

申请号：US14717218

申请日：2015-05-20

申请人： International Business Machines Corporation

发明人： Tak H. Ning

IPC分类号： G11C11/00 ,  G11C11/411 ,  H01L27/11

CPC分类号： G11C11/416 ,  G11C11/411 ,  G11C11/4116 ,  H01L21/8228 ,  H01L21/8229 ,  H01L27/1025 ,  H01L27/11

摘要： A complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. 'The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.

摘要翻译： 互补横向双极型SRAM器件。 该器件包括：第一组和第二组横向双极晶体管，形成相应的第一反相器器件和第二反相器器件，第一和第二反相器器件交叉耦合以存储逻辑状态。 在每个所述第一和第二组中，第一双极晶体管是PNP型双极晶体管，第二双极晶体管是NPN型双极晶体管，每个所述NPN型双极晶体管具有基极端子，第一发射极端子，第二发射极 端子和集电极端子。 每个第一和第二逆变器装置的PNP型晶体管的发射极端子电耦合在一起并接收第一施加的字线电压。 所述第一反相器和第二反相器装置的每个所述NPN晶体管的第一发射极端子电耦合在一起并接收第二施加电压。 “所述第一反相器的一个NPN双极晶体管的第二发射极端子电耦合到第一位线导体，并且所述第二逆变器器件的NPN双极晶体管的第二发射极端子电耦合到第二位线。

公开(公告)号：US09305633B2

公开(公告)日：2016-04-05

申请号：US14283120

申请日：2014-05-20

申请人： STMicroelectronics International N.V.

发明人： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC分类号： G11C11/00 ,  G11C11/412 ,  G11C5/02 ,  G11C11/415 ,  G11C11/413 ,  G11C11/419 ,  G11C11/416 ,  G11C11/411

CPC分类号： G11C11/412 ,  G11C5/02 ,  G11C8/16 ,  G11C11/4116 ,  G11C11/413 ,  G11C11/415 ,  G11C11/416 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104

摘要： Embodiments include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts.

摘要翻译： 实施例包括SRAM单元阵列，SRAM单元及其形成方法。 一个实施例是包括多个重叠矩形区域的静态随机存取存储器（SRAM）单元阵列。 每个重叠矩形区域包括整个第一SRAM单元，矩形区域的第一角区域中的第二相邻SRAM单元的一部分和矩形区域的第二角区域中的第三相邻SRAM单元的一部分， 第二角区域与第一角区域相对。 实施例还包括多指细胞布局。

公开(公告)号：US20150302917A1

公开(公告)日：2015-10-22

申请号：US14283120

申请日：2014-05-20

申请人： STMICROELECTRONICS INTERNATIONAL N.V.

发明人： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC分类号： G11C11/412 ,  G11C5/02

CPC分类号： G11C11/412 ,  G11C5/02 ,  G11C8/16 ,  G11C11/4116 ,  G11C11/413 ,  G11C11/415 ,  G11C11/416 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104

摘要： Embodiments of the present disclosure include an array of SRAM cells, an SRAM cell, and methods of forming the same. An embodiment is an array of static random access memory (SRAM) cells including a plurality of overlapping rectangular regions. Each of overlapping rectangular regions including an entire first SRAM cell, a portion of a second adjacent SRAM cell in a first corner region of the rectangular region, and a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being opposite the first corner region. Embodiments also include multi-finger cell layouts.

摘要翻译： 本公开的实施例包括SRAM单元的阵列，SRAM单元及其形成方法。 一个实施例是包括多个重叠矩形区域的静态随机存取存储器（SRAM）单元阵列。 每个重叠矩形区域包括整个第一SRAM单元，矩形区域的第一角区域中的第二相邻SRAM单元的一部分和矩形区域的第二角区域中的第三相邻SRAM单元的一部分， 第二角区域与第一角区域相对。 实施例还包括多指细胞布局。

公开(公告)号：US08009459B2

公开(公告)日：2011-08-30

申请号：US12346173

申请日：2008-12-30

申请人： Cheng-Hsu Wu ,  David Yen ,  Tsai-Hsin Lai

发明人： Cheng-Hsu Wu ,  David Yen ,  Tsai-Hsin Lai

IPC分类号： G11C11/24

CPC分类号： G11C11/416 ,  G11C11/405

摘要： A memory cell includes a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.

摘要翻译： 存储单元包括耦合在存储节点和写位线之间的写入存取晶体管，并且响应于写字线上的电压在写周期期间有效; 读取存取晶体管，耦合在读取字线和读取位线之间，并且响应于存储节点处的电压在读取周期期间有效; 以及耦合在读取字线和存储节点之间的存储电容器。 还公开了用于操作存储器单元的方法。

公开(公告)号：US07929333B2

公开(公告)日：2011-04-19

申请号：US12343996

申请日：2008-12-24

申请人： Atsushi Kawasumi

发明人： Atsushi Kawasumi

IPC分类号： G11C11/00

CPC分类号： G11C11/416 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412

摘要： A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines.

摘要翻译： 半导体存储器件包括：子阵列，其包括多个存储单元，每个存储单元保持布置在其中的数据; 包括布置在其中的多个子阵列的存储单元阵列; 成对位线，包括连接到每个子阵列的第一位线和第二位线; 以及写入/读取电路，被布置为对应于每个子阵列，将数据写入子阵列，以及从子阵列读取数据，其中一对子阵列和写/读电路沿着配对重复排列 位线，允许数据通过写/读电路和配对位线传输。