知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.028 秒)

    Structure for reducing pre-charge voltage for static random-access memory arrays
    4.
    发明授权
    Structure for reducing pre-charge voltage for static random-access memory arrays 有权
    用于降低静态随机存取存储器阵列的预充电电压的结构

    公开(公告)号：US09431098B1

    公开(公告)日：2016-08-30

    申请号：US14822089

    申请日：2015-08-10

    申请人： International Business Machines Corporation

    发明人： Alexander Fritsch ,  Amira Rozenfeld ,  Rolf Sautter ,  Dieter Wendel

    IPC分类号： G11C5/06 ,  G11C11/419

    CPC分类号： G11C11/416 ,  G06F17/5045 ,  G06F17/5081 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/418 ,  G11C11/419 ,  H01L23/528 ,  H01L27/1104

    摘要： A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

    摘要翻译： 可以提供SRAM单元组的存储单元布置，其中在每个组中，多个SRAM单元通过至少一个公共局部位线连接到本地读取放大器的输入。 放大器的输出连接到共享的全局位线。 全局位线连接到预充电电路，并且预充电电路适于在读取数据之前用可编程预充电电压对全局位线进行预充电。 预充电电路包括限幅器电路，其包括连接到全局位线的预充电调节器电路，以用可编程预充电电压对全局位线预充电;以及评估和转换电路，连接到 预充电调节器电路和全局位线，以补偿全局位线的泄漏电流，而不改变其电压电平。

    LAYOUT OF A MEMORY CELL OF AN INTEGRATED CIRCUIT
    5.
    发明申请
    LAYOUT OF A MEMORY CELL OF AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200320174A1

    公开(公告)日：2020-10-08

    申请号：US16378079

    申请日：2019-04-08

    申请人： International Business Machines Corporation

    发明人： Rolf Sautter ,  Amira Rozenfeld ,  Shankar Kalyanasundaram ,  Ananth Nag Raja Darla ,  Rajesh Veerabhadraiah

    IPC分类号： G06F17/50 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

    摘要： Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.

    DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-ACCESS MEMORY ARRAYS
    8.
    发明申请
    DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-ACCESS MEMORY ARRAYS 有权
    用于降低静态随机存取存储器阵列的预充电电压的设计结构

    公开(公告)号：US20170047111A1

    公开(公告)日：2017-02-16

    申请号：US15155223

    申请日：2016-05-16

    申请人： International Business Machines Corporation

    发明人： Alexander Fritsch ,  Amira Rozenfeld ,  Rolf Sautter ,  Dieter Wendel

    IPC分类号： G11C11/419

    CPC分类号： G11C11/416 ,  G06F17/5045 ,  G06F17/5081 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/418 ,  G11C11/419 ,  H01L23/528 ,  H01L27/1104

    摘要： A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

    摘要翻译： 可以提供SRAM单元组的存储单元布置，其中在每个组中，多个SRAM单元通过至少一个公共局部位线连接到本地读取放大器的输入。 放大器的输出连接到共享的全局位线。 全局位线连接到预充电电路，并且预充电电路适于在读取数据之前用可编程预充电电压对全局位线进行预充电。 预充电电路包括限幅器电路，其包括连接到全局位线的预充电调节器电路，以用可编程预充电电压对全局位线预充电;以及评估和转换电路，连接到 预充电调节器电路和全局位线，以补偿全局位线的泄漏电流，而不改变其电压电平。

    Content addressable memory device
    10.
    发明授权
    Content addressable memory device 有权
    内容可寻址存储设备

    公开(公告)号：US09536608B1

    公开(公告)日：2017-01-03

    申请号：US14943152

    申请日：2015-11-17

    申请人： International Business Machines Corporation

    发明人： Alexander Fritsch ,  Amira Rozenfeld ,  Gordon B. Sapp ,  Rolf Sautter

    IPC分类号： G11C15/00 ,  G11C15/04

    CPC分类号： G11C15/04

    摘要： Disclosed aspects include a content addressable memory device comprising at least two memory banks connectable to a global search line. Each memory bank comprises at least two content addressable memory cells. Each content addressable memory cell can store one bit. Each content addressable memory cell is coupled to a respective local search line. Aspects include a bank connection circuitry configured for coupling the global search line to the local search lines in dependence of a bank prediction signal line. The bank connection circuitry of the content addressable memory device may comprise bank hold circuitry for storing a search value transmitted by the global search line.

    摘要翻译： 公开的方面包括内容可寻址存储器设备，其包括可连接到全局搜索线的至少两个存储体。 每个存储体包括至少两个可内容寻址的存储单元。 每个内容可寻址存储单元可以存储一位。 每个内容可寻址存储器单元耦合到相应的本地搜索行。 方面包括配置成根据银行预测信号线将全局搜索线耦合到局部搜索线的存储体连接电路。 内容可寻址存储设备的存储体连接电路可以包括用于存储由全局搜索行发送的搜索值的存储体保持电路。