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    High density array, in memory computing
    1.
    发明授权
    High density array, in memory computing 有权

    公开(公告)号：US11798615B2

    公开(公告)日：2023-10-24

    申请号：US17721956

    申请日：2022-04-15

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Tanmoy Roy

    IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

    CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091 ,  G11C11/4096

    Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

    Elements for in-memory compute
    2.
    发明授权
    Elements for in-memory compute 有权

    公开(公告)号：US11474788B2

    公开(公告)日：2022-10-18

    申请号：US16890870

    申请日：2020-06-02

    Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover ,  Giuseppe Desoli

    IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

    Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

    Low voltage, master-slave flip-flop
    3.
    发明授权
    Low voltage, master-slave flip-flop 有权

    公开(公告)号：US10277207B1

    公开(公告)日：2019-04-30

    申请号：US15892308

    申请日：2018-02-08

    Applicant: STMicroelectronics International N.V.

    Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Anuj Grover ,  Deepak Kumar Bihani ,  Tanmoy Roy ,  Tanuj Agrawal

    IPC: H03K3/00 ,  H03K3/3562 ,  G11C11/412

    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

    MEMORY WITH AN ASSIST DETERMINATION CONTROLLER AND ASSOCIATED METHODS
    4.
    发明申请
    MEMORY WITH AN ASSIST DETERMINATION CONTROLLER AND ASSOCIATED METHODS 有权
    记忆与辅助确定控制器及相关方法

    公开(公告)号：US20140293723A1

    公开(公告)日：2014-10-02

    申请号：US13852222

    申请日：2013-03-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

    IPC: G11C7/06

    CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

    Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

    Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。

    In-memory compute array with integrated bias elements
    5.
    发明授权
    In-memory compute array with integrated bias elements 有权

    公开(公告)号：US12243584B2

    公开(公告)日：2025-03-04

    申请号：US18167580

    申请日：2023-02-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Tanmoy Roy ,  Nitin Chawla

    IPC: G11C11/41 ,  G11C11/419 ,  H10B10/00

    Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.

    In-memory compute array with integrated bias elements
    6.
    发明授权
    In-memory compute array with integrated bias elements 有权

    公开(公告)号：US11605424B2

    公开(公告)日：2023-03-14

    申请号：US17375945

    申请日：2021-07-14

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Anuj Grover ,  Tanmoy Roy ,  Nitin Chawla

    IPC: G11C11/41 ,  G11C11/419 ,  H01L27/11

    Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

    High-density array, in memory computing
    8.
    发明授权
    High-density array, in memory computing 有权

    公开(公告)号：US11335397B2

    公开(公告)日：2022-05-17

    申请号：US16994488

    申请日：2020-08-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj Grover ,  Tanmoy Roy

    IPC: G11C16/04 ,  G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

    Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

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