公开(公告)号：US12237023B2

公开(公告)日：2025-02-25

申请号：US17134010

申请日：2020-12-24

Applicant: Intel NDTM US LLC

Inventor： Tarek Ahmed Ameen Beshari ,  Shantanu R. Rajwade ,  Matin Amani ,  Narayanan Ramanan

IPC: G11C16/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.