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1.发明授权公开(公告)号：US12237023B2
公开(公告)日：2025-02-25
申请号：US17134010
申请日：2020-12-24
Applicant: Intel NDTM US LLC
Inventor： Tarek Ahmed Ameen Beshari , Shantanu R. Rajwade , Matin Amani , Narayanan Ramanan
Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.
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公开(公告)号：US12051469B2
公开(公告)日：2024-07-30
申请号：US17825960
申请日：2022-05-26
Applicant: Intel NDTM US LLC
Inventor： Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/32
Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
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