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公开(公告)号：US20230024668A1
公开(公告)日：2023-01-26
申请号：US17550234
申请日：2021-12-14
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Min Su KIM , Hyun Chul CHO
Abstract: A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.
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公开(公告)号：US20220066870A1
公开(公告)日：2022-03-03
申请号：US17190707
申请日：2021-03-03
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Se Chun PARK
Abstract: The present technology relates to an electronic device. A memory system for increasing reliability of data includes a memory device including a plurality of pages, and a memory controller configured to correct an error in read data obtained by reading a selected page among the plurality of pages, and determine whether to perform a refresh operation on the selected page based on a number of error bits included in the read data. The memory controller comprises a normal read operation controller configured to control a read operation on the selected page and determine the number of error bits in the read data, an error correction performance component configured to correct the read data, and a data recovery controller configured to control the refresh operation on the selected page based on the number of error bits in the read data when the error in the read data is corrected.
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公开(公告)号：US20210118479A1
公开(公告)日：2021-04-22
申请号：US16892821
申请日：2020-06-04
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Gwan PARK
Abstract: A memory device includes a plurality of memory cell arrays each configured to include a plurality of memory cells, a plurality of peripheral circuits each configured to perform operations on the plurality of memory cell arrays, a plurality of control logics configured to control the plurality of peripheral circuits, and a control logic selector configured to activate at least one control logic among the plurality of control logics according to a type of a command received from the memory controller.
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公开(公告)号：US20240420768A1
公开(公告)日：2024-12-19
申请号：US18485040
申请日：2023-10-11
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Won Jun KANG
Abstract: A semiconductor device includes a memory cell connected to a word line and a bit line. The semiconductor device also includes a line driving circuit configured to apply a program voltage to the word line. The semiconductor device further includes a page buffer comprising a plurality of latches comprising at least one dynamic latch and at least one static latch and configured to control a voltage level of the bit line after the start of a program operation. The semiconductor device additionally includes a control circuit configured to control the page buffer to program, into the memory cell, data that have been stored in the static latch or store the data in the dynamic latch based on a temperature of the semiconductor device, when receiving a pause command during the program operation.
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公开(公告)号：US20240013821A1
公开(公告)日：2024-01-11
申请号：US18074280
申请日：2022-12-02
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Jeong Hwan KIM , Moon Soo SUNG
CPC classification number: G11C7/1096 , G11C7/1069 , G11C7/12 , G11C7/1039
Abstract: Provided herein may be a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device may include a memory cell array, a read and write circuit, and a control logic. The memory cell array may include a plurality of nonvolatile memory cells. The read and write circuit may be configured to perform a program operation or a read operation on nonvolatile memory cells that are selected from among the plurality of nonvolatile memory cells. The control logic may be configured to control an operation of the read and write circuit. The read and write circuit may include at least one capacitor configured to store bit data.
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Patent Agency Ranking
公开(公告)号：US20200381066A1
公开(公告)日：2020-12-03
申请号：US16733698
申请日：2020-01-03
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Sung Bak KIM
Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device may include memory cells configured to store data, a peripheral circuit configured to perform program and read operation on memory cells selected from among the memory cells, and a refresh controller configured to include a counter and a refresh manager, wherein the counter is configured to count a number of memory cells which are in an erased state or a programmed state by performing a read operation on the selected memory cells using a reference read voltage, and the refresh manager is configured to compare a read count indicating the counted number of memory cells, with a preset reference count, to determine whether to shift the reference read voltage and to control the peripheral circuit so that the program operation is performed using a voltage different than a program voltage by a step voltage.
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公开(公告)号：US20250048629A1
公开(公告)日：2025-02-06
申请号：US18507910
申请日：2023-11-13
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Sung Lae OH
Abstract: A semiconductor device may include: a capacitor including a first source electrode, a second source electrode connected in common to a plurality of second access lines, each of the second access lines spaced apart from one another and located on different layers, and a first channel structure located on the first source electrode and penetrating through the plurality of second access lines; and at least one cell string located between a source line and a first access line, the at least one cell string including a second channel structure penetrating through the plurality of second access lines, the plurality of second access lines electrically separated from each other.
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公开(公告)号：US20210049067A1
公开(公告)日：2021-02-18
申请号：US16825841
申请日：2020-03-20
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Ki Chang GWON
Abstract: The present technology relates to an electronic device. A memory device performing efficient soft decoding by reducing the number of data provided to a memory controller includes a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer includes a plurality of latches and a read data operating component configured to generate a soft bit by logically operating soft data, which are data read from the memory cell array, and to provide the soft bit to a memory controller, in a second read operation performed when a first read operation has failed.
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公开(公告)号：US20250054554A1
公开(公告)日：2025-02-13
申请号：US18430892
申请日：2024-02-02
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Chang Hee LEE , Hyun Chul CHO
Abstract: According to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage used for an operation on each of the plurality of planes according to a first clock signal having a first cycle; page buffers each configured to store pass data representing whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to, based on a number of the pass data received from the page buffers, control the charge pump to generate the operating voltage according to a second clock signal having a second cycle that is longer than the first cycle.
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公开(公告)号：US20240395336A1
公开(公告)日：2024-11-28
申请号：US18496735
申请日：2023-10-27
Applicant: SK hynix Inc.
Inventor： Won Jae CHOI , Ji Hoon LIM
Abstract: Provided herein is a memory device for driving charge pumps respectively included in memory dies. The memory device includes a first memory die including a first charge pump and a first pump control circuit, and a second memory die including a second charge pump coupled to the first charge pump through a pump line and a second pump control circuit coupled to the first pump control circuit through a control line. The first pump control circuit is configured to control the first charge pump to perform a pump operation of generating a pump voltage in response to a command received by the first memory die, and output an operation alarm signal through the control line, and the second pump control circuit is configured to control the second charge pump to perform the pump operation in response to the operation alarm signal.
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