RECEIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME

    公开(公告)号:US20240347085A1

    公开(公告)日:2024-10-17

    申请号:US18473837

    申请日:2023-09-25

    CPC classification number: G11C7/20 G11C7/106 G11C7/1063 G11C7/222

    Abstract: A receiver includes a buffer configured to generate an internal data signal by comparing a received data signal with a reference voltage, a decision feedback equalizer configured to generate a sampled signal based on a present value of the internal data signal and on a feedback signal, and configured to provide one of the sampled signal or a first logic level as the feedback signal based on a reset control signal, the sampled signal corresponding to a previous value of the internal data signal, a deserializer configured to generate an output data by deserializing the sampled signal, and a reset control circuit configured to generate the reset control signal based on operating information associated with a write operation of the data signal and configured to provide the reset control signal to the decision feedback equalizer.

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