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公开(公告)号：US12019884B2
公开(公告)日：2024-06-25
申请号：US17651215
申请日：2022-02-15
发明人： Luca Porzio , Roberto Izzi , Christian M. Gyllenskog , Giuseppe Cariello , Jonathan S. Parry , Reshmi Basu
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F12/0238 , G06F2212/7201
摘要： Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.
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公开(公告)号：US20240053925A1
公开(公告)日：2024-02-15
申请号：US17888325
申请日：2022-08-15
发明人： Reshmi Basu , Jonathan S. Parry , Nitul Gohain
CPC分类号： G06F3/0659 , G06F3/0634 , G06F3/0679 , G06F3/0604 , G06F12/0253
摘要： Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
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公开(公告)号：US20240020986A1
公开(公告)日：2024-01-18
申请号：US18478424
申请日：2023-09-29
发明人： Reshmi Basu
摘要： Methods, systems, and apparatuses related to autonomous vehicle object detection are described. A method can include receiving, by an autonomous vehicle, an indication that the autonomous vehicle has entered a network coverage zone generated by a base station and performing an operation to reallocate computing resources between a plurality of different types of memory devices associated with the autonomous vehicle in response to receiving the indication. The method can further include capturing, by the autonomous vehicle, data corresponding to an unknown object disposed within a sight line of the autonomous vehicle and performing, using the reallocated computing resources, an operation involving the data corresponding to the unknown object to classify the unknown object.
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公开(公告)号：US11853558B2
公开(公告)日：2023-12-26
申请号：US17718386
申请日：2022-04-12
发明人： David A. Palmer , Jonathan S. Parry , Reshmi Basu
IPC分类号： G06F3/06
CPC分类号： G06F3/0617 , G06F3/0653 , G06F3/0679
摘要： Apparatuses and methods can be related power down workload estimations using artificial neural networks. Workload estimation can include predicting a duration of a subsequent power down event of the memory device. A quantity of maintenance operations to be performed on the memory device, may be predicted based on the predicted duration of the subsequent power down event, when the memory device is powered on after the subsequent power down event using an artificial neural network. The quantity of maintenance operations may be performed on the memory device prior to the subsequent power down event of the memory device.
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公开(公告)号：US20230289283A1
公开(公告)日：2023-09-14
申请号：US18110040
申请日：2023-02-15
发明人： Reshmi Basu
IPC分类号： G06F12/02
CPC分类号： G06F12/0223
摘要： A method includes writing a first codeword to a first set of contiguous partitions in a first memory die of a memory device. The method further includes writing a first portion of a second codeword to a second set of contiguous partitions in the first memory die of the memory device and writing a second portion of the second codeword to a first set of contiguous partitions in a second memory die of the memory device. The method also includes writing a third codewords to a second set of contiguous partitions in the second memory die of the memory device.
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公开(公告)号：US20230214126A1
公开(公告)日：2023-07-06
申请号：US17718386
申请日：2022-04-12
发明人： David A. Palmer , Jonathan S. Parry , Reshmi Basu
IPC分类号： G06F3/06
CPC分类号： G06F3/0617 , G06F3/0653 , G06F3/0679
摘要： Apparatuses and methods can be related power down workload estimations using artificial neural networks. Workload estimation can include predicting a duration of a subsequent power down event of the memory device. A quantity of maintenance operations to be performed on the memory device, may be predicted based on the predicted duration of the subsequent power down event, when the memory device is powered on after the subsequent power down event using an artificial neural network. The quantity of maintenance operations may be performed on the memory device prior to the subsequent power down event of the memory device.
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公开(公告)号：US20230197119A1
公开(公告)日：2023-06-22
申请号：US17675468
申请日：2022-02-18
发明人： Ryan G. Fisher , Arvin Daniel A. Daguro , Daniel R. Loughmiller , Noel Marquez , Reshmi Basu , Kenneth Koenig
摘要： A method includes performing a first operation to program data to a group of memory cells of a memory device, wherein the data comprises host data and a bit pattern indicative of a first temperature of the group of memory cells and receiving a signal to perform a second operation to read the host data from the group of memory cells. The method further includes determining, responsive to receipt of the signal, whether a second temperature of the group of memory cells is outside a threshold temperature differential that is based on the bit pattern indicative of the first temperature of the group of memory cells, applying a voltage offset signal to the group of memory cells responsive to a determination that the second temperature of the group of memory cells is outside the threshold temperature differential, and performing the second operation to read the host data from the group of memory cells subsequent to application of the voltage offset signal to the group of memory cells.
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公开(公告)号：US11605434B1
公开(公告)日：2023-03-14
申请号：US17462305
申请日：2021-08-31
发明人： Jonathan S. Parry , Jeffrey S. McNeil , Giuseppe Cariello , Kishore Kumar Muchherla , Reshmi Basu
摘要： Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.
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公开(公告)号：US11604725B2
公开(公告)日：2023-03-14
申请号：US17007006
申请日：2020-08-31
发明人： Reshmi Basu
IPC分类号： G06F12/02
摘要： A hybrid addressing scheme in which a maximum of three codeword groups are utilized across pairs of memory dice and/or access rows of the memory sub-system or memory device is provided. By controlling the arrangement of such codewords, it can be possible to group codewords such that disturb effects can be reduced. For example, codewords can be grouped in a symmetrical manner with respect to the memory dice of a memory device, which can allow for simplified codeword addressing.
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公开(公告)号：US20230046313A1
公开(公告)日：2023-02-16
申请号：US17399889
申请日：2021-08-11
发明人： Giuseppe Cariello , Reshmi Basu
IPC分类号： G06F3/06
摘要： Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.
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