Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.