公开(公告)号：US12068194B2

公开(公告)日：2024-08-20

申请号：US18364286

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/7681 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US11810857B2

公开(公告)日：2023-11-07

申请号：US17001917

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Chih-Yi Chang ,  Ming-Hsiao Hsieh ,  Wei-Hsiang Chan ,  Ya-Lien Lee ,  Chien Chung Huang ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76877

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

公开(公告)号：US20240363403A1

公开(公告)日：2024-10-31

申请号：US18766300

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/7681 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US20220367376A1

公开(公告)日：2022-11-17

申请号：US17815026

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Huan-Yu Shih ,  Wen-Hsuan Chen ,  Cheng-Lun Tsai ,  Ya-Lien Lee ,  Cheng-Hui Weng ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Yao-Min Liu

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

公开(公告)号：US20220084937A1

公开(公告)日：2022-03-17

申请号：US17143496

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Min Liu ,  Chia-Pang Kuo ,  Chien Chung Huang ,  Chih-Yi Chang ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

公开(公告)号：US20240006234A1

公开(公告)日：2024-01-04

申请号：US18364286

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/7681 ,  H01L23/53238 ,  H01L23/5226 ,  H01L21/76879

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US11837500B2

公开(公告)日：2023-12-05

申请号：US17809919

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/7681 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US11527476B2

公开(公告)日：2022-12-13

申请号：US17143496

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Min Liu ,  Chia-Pang Kuo ,  Chien Chung Huang ,  Chih-Yi Chang ,  Ya-Lien Lee ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

公开(公告)号：US20220328347A1

公开(公告)日：2022-10-13

申请号：US17809919

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US20230369224A1

公开(公告)日：2023-11-16

申请号：US18358803

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pang Kuo ,  Chih-Yi Chang ,  Ming-Hsiao Hsieh ,  Wei-Hsiang Chan ,  Ya-Lien Lee ,  Chien Chung Huang ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76877 ,  H01L21/76804 ,  H01L21/76846

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.