- 专利标题: SELECTIVE DEPOSITION OF METAL BARRIER IN DAMASCENE PROCESSES
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申请号: US18766300申请日: 2024-07-08
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公开(公告)号: US20240363403A1公开(公告)日: 2024-10-31
- 发明人: Chia-Pang Kuo , Ya-Lien Lee , Chieh-Yi Shen
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 分案原申请号: US16213622 2018.12.07
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522 ; H01L23/532
摘要:
A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.
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