Invention Grant
- Patent Title: Selective deposition of metal barrier in damascene processes
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Application No.: US18364286Application Date: 2023-08-02
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Publication No.: US12068194B2Publication Date: 2024-08-20
- Inventor: Chia-Pang Kuo , Ya-Lien Lee , Chieh-Yi Shen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US16213622 2018.12.07
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.
Public/Granted literature
- US20240006234A1 Selective Deposition of Metal Barrier in Damascene Processes Public/Granted day:2024-01-04
Information query
IPC分类: