公开(公告)号：US20230037554A1

公开(公告)日：2023-02-09

申请号：US17395915

申请日：2021-08-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHU-WEI LI ,  YU-CHEN CHAN ,  MENG-PEI LU ,  SHIN-YI YANG ,  MING-HAN LEE

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

摘要： A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric layer disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure, wherein the interconnect structure laterally connects to at least one edge of the 2D conductive structure.

公开(公告)号：US20220359378A1

公开(公告)日：2022-11-10

申请号：US17814844

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-PEI LU ,  SHIN-YI YANG ,  SHU-WEI LI ,  CHIN-LUNG CHUNG ,  MING-HAN LEE

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

摘要： A method for forming a semiconductor structure includes following operations. A hybrid layered structure is formed. The hybrid layered structure includes at least a 2D material layer and a first 3D material layer. Portions of the hybrid layered structure are removed to form a plurality of conductive features and at least an opening between the conductive features. A dielectric material is formed to fill the opening and to form an air gap sealed within.

公开(公告)号：US20240088042A1

公开(公告)日：2024-03-14

申请号：US18152778

申请日：2023-01-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHU-WEI LI ,  HAN-TANG HUNG ,  YU-CHEN CHAN ,  CHIEN-HSIN HO ,  SHIN-YI YANG ,  MING-HAN LEE ,  SHAU-LIN SHUE

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53276 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329

摘要： A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.

公开(公告)号：US20160218035A1

公开(公告)日：2016-07-28

申请号：US15088134

申请日：2016-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHIN-YI YANG ,  HSI-WEN TIEN ,  MING-HAN LEE ,  HSIANG-HUAN LEE ,  SHAU-LIN SHUE

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522

CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76844 ,  H01L21/76876 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53276 ,  H01L23/53295 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

公开(公告)号：US20240363538A1

公开(公告)日：2024-10-31

申请号：US18768002

申请日：2024-07-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHU-WEI LI ,  YU-CHEN CHAN ,  MENG-PEI LU ,  SHIN-YI YANG ,  MING-HAN LEE

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53276 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5328

摘要： A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric structure disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure. The interconnect structure laterally contacts the 2D conductive structure.

公开(公告)号：US20220068799A1

公开(公告)日：2022-03-03

申请号：US17008141

申请日：2020-08-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-PEI LU ,  SHIN-YI YANG ,  SHU-WEI LI ,  CHIN-LUNG CHUNG ,  MING-HAN LEE

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

摘要： A semiconductor structure includes a substrate, a plurality of conductive features disposed over the substrate, and an isolation structure between conductive features and separating the conductive features from each other. Each of the conductive features includes a first metal layer and a 2D material layer. Another semiconductor structure includes a first conductive feature, a dielectric structure over the first conductive feature, a second conductive feature in the dielectric structure and coupled to the first conductive feature, and a conductive line over and coupled to the second conductive feature. In some embodiments, the conductive line includes a first 3D material layer, a first 2D material layer, and a second 3D material layer. The first 2D material layer is disposed between the first 3D material layer and the second 3D material layer.

公开(公告)号：US20150325522A1

公开(公告)日：2015-11-12

申请号：US14271726

申请日：2014-05-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： CHING-FU YEH ,  MING-HAN LEE

IPC分类号： H01L23/532 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76882 ,  C23C14/046 ,  C23C14/345 ,  C23C14/5826 ,  H01L21/2855 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/76807 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor comprises: providing a substrate; forming an opening in a dielectric layer disposed over the substrate; providing a target with a first type atoms; ionizing the first type atoms provided from the target; providing a bias to the substrate for controlling the moving paths of the ionized first type atoms thereby directing the ionized first type atoms in the opening; and forming a first conductive structure from bottom of the opening with the ionized first type atoms under a pre-determined frequency and a pre-determined pressure.

摘要翻译： 一种制造半导体的方法包括：提供衬底; 在设置在所述基板上的电介质层中形成开口; 提供具有第一类原子的靶; 电离从靶提供的第一类型原子; 向衬底提供偏置以控制电离的第一类型原子的移动路径，从而将离子化的第一类型原子引导到开口中; 以及在预定频率和预定压力下，以离子化的第一类型原子从开口的底部形成第一导电结构。

公开(公告)号：US20150270225A1

公开(公告)日：2015-09-24

申请号：US14222181

申请日：2014-03-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHIN-YI YANG ,  HSI-WEN TIEN ,  MING-HAN LEE ,  HSIANG-HUAN LEE ,  SHAU-LIN SHUE

IPC分类号： H01L23/532 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76844 ,  H01L21/76876 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53276 ,  H01L23/53295 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

摘要翻译： 本公开提供了一种互连结构，包括衬底，衬底上的第一导电特征，第一导电特征之上的第二导电特征，以及围绕第一导电特征和第二导电特征的介电层。 第一导电特征的宽度和第二导电特征的宽度在10nm和50nm之间。 本公开还提供一种用于制造互连结构的方法，包括（1）在电介质层中形成通孔和线沟槽，（2）在通孔开口中形成一维导电特征，（3）形成 在线沟槽的侧壁上的保形催化剂层，线沟槽的底部和一维导电特征的顶部，以及（4）从线沟槽的底部和顶部的去除保形催化剂层 一维导电特征。