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公开(公告)号：US11800707B2
公开(公告)日：2023-10-24
申请号：US16881268
申请日：2020-05-22
发明人： Shuangshuang Peng , Jingjing Geng , Jiajia Wu , Tuo Li
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.
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公开(公告)号：US11711921B2
公开(公告)日：2023-07-25
申请号：US17084378
申请日：2020-10-29
发明人： Zhen Guo , Jingjing Geng , Bin Yuan , Jiajia Wu , Xiangning Wang , Zhu Yang , Chen Zuo
IPC分类号： H10B43/27 , H01L21/762 , H01L23/544
CPC分类号： H10B43/27 , H01L21/76229 , H01L23/544 , H01L2223/54426
摘要： Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.
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公开(公告)号：US11990506B2
公开(公告)日：2024-05-21
申请号：US17084346
申请日：2020-10-29
IPC分类号： H01L29/06 , G11C8/14 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H01L29/0649 , G11C8/14 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.
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公开(公告)号：US20220077181A1
公开(公告)日：2022-03-10
申请号：US17084378
申请日：2020-10-29
发明人： Zhen Guo , Jingjing Geng , Bin Yuan , Jiajia Wu , Xiangning Wang , Zhu Yang , Chen Zuo
IPC分类号： H01L27/11582 , H01L23/544 , H01L21/762
摘要： Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.
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公开(公告)号：US20210305277A1
公开(公告)日：2021-09-30
申请号：US17329103
申请日：2021-05-24
发明人： Shuangshuang Peng , Jingjing Geng , Jiajia Wu , Tuo Li
IPC分类号： H01L27/11582 , H01L27/1157
摘要： In certain aspects, a first opening extending vertically through a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A high-k dielectric layer and a channel sacrificial layer free of polysilicon are subsequently formed along a sidewall of the first opening. A second opening extending vertically through a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck is formed to expose the channel sacrificial layer in the first opening. The channel sacrificial layer is removed in the first opening. A memory film and a semiconductor channel are subsequently formed over the high-k dielectric layer along sidewalls of the first and second openings.
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6.发明公开公开(公告)号：US20230301106A1
公开(公告)日：2023-09-21
申请号：US18202073
申请日：2023-05-25
发明人： Zhen Guo , Jingjing Geng , Bin Yuan , Jiajia Wu , Xiangning Wang , Zhu Yang , Chen Zuo
IPC分类号： H10B43/27 , H01L21/762 , H01L23/544
CPC分类号： H10B43/27 , H01L21/76229 , H01L23/544 , H01L2223/54426
摘要： Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.
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公开(公告)号：US20220077283A1
公开(公告)日：2022-03-10
申请号：US17084346
申请日：2020-10-29
IPC分类号： H01L29/06 , H01L27/11519 , H01L27/11524 , H01L27/11556 , G11C8/14 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.
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公开(公告)号：US20210305274A1
公开(公告)日：2021-09-30
申请号：US16881268
申请日：2020-05-22
发明人： Shuangshuang Peng , Jingjing Geng , Jiajia Wu , Tuo Li
IPC分类号： H01L27/11582 , H01L27/1157
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.
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9.发明公开公开(公告)号：US20240194606A1
公开(公告)日：2024-06-13
申请号：US18092105
申请日：2022-12-30
发明人： Jiajia Wu , Wei Xu , Bin Yuan , Lei Xue , Zongliang Huo
IPC分类号： H01L23/535 , H10B43/27
CPC分类号： H01L23/535 , H01L27/11582
摘要： A semiconductor structure includes a stack structure, first gate isolation structures, and conductive structures. The stack structure includes gate layers and first dielectric layers disposed alternately. The first gate isolation structures extend along a first direction, and the first gate isolation structures are arranged at intervals along a second direction and divide the stack structure into at least one block comprising a memory region and a connection region that are distributed along the first direction. The conductive structures are located in the connection region, and orthographic projections of upper ends of at least two conductive structures on a reference plane at least partially overlap. The reference plane is perpendicular to the second direction, and the first direction is perpendicular to the second direction.
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公开(公告)号：US20240170389A1
公开(公告)日：2024-05-23
申请号：US17991050
申请日：2022-11-21
发明人： Jiajia Wu , Bin Yuan , Zongke Xu , Zhen Guo , Beibei Li , Xiangning Wang , Zhu Yang , Qiangwei Zhang , Zongliang Huo
IPC分类号： H01L23/522 , H01L27/11556 , H01L27/11582
CPC分类号： H01L23/5221 , H01L27/11556 , H01L27/11582
摘要： In certain aspects, a three-dimensional (3D) memory device includes a stack structure including alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions, and bridge structures connecting the two core regions and extending through the staircase region in a first direction. A first bridge structure of the bridge structures includes at least two current paths between the two core regions.
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