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    INTEGRATED CIRCUIT INCLUDING FLIP-FLOP AND COMPUTING SYSTEM FOR DESIGNING THE INTEGRATED CIRCUIT
    1.
    发明申请
    INTEGRATED CIRCUIT INCLUDING FLIP-FLOP AND COMPUTING SYSTEM FOR DESIGNING THE INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220385277A1

    公开(公告)日：2022-12-01

    申请号：US17696086

    申请日：2022-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungman LIM ,  Minsu KIM ,  Ahreum KIM

    IPC: H03K3/037 ,  H03K17/687

    Abstract: An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.

    VOLTAGE LEVEL SHIFTER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
    2.
    发明申请
    VOLTAGE LEVEL SHIFTER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20220271742A1

    公开(公告)日：2022-08-25

    申请号：US17564915

    申请日：2021-12-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chanhee PARK ,  Ahreum KIM ,  Minsu KIM

    IPC: H03K3/356 ,  H01L27/02

    Abstract: A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220392532A1

    公开(公告)日：2022-12-08

    申请号：US17578840

    申请日：2022-01-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ansoo PARK ,  Ahreum KIM ,  Homoon SHIN

    IPC: G11C16/08 ,  G11C16/30

    Abstract: A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type. At least one of the low-voltage elements is in a second well region surrounding the first well region and doped with impurities having a second conductivity-type, different from the first conductivity-type.

    ACTIVE RESISTOR ARRAY OF SEMICONDUCTOR MEMORY DEVICE
    4.
    发明公开
    ACTIVE RESISTOR ARRAY OF SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230328977A1

    公开(公告)日：2023-10-12

    申请号：US17883842

    申请日：2022-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ansoo PARK ,  Ahreum KIM

    IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/08

    CPC classification number: H01L27/11524 ,  H01L27/0802 ,  H01L27/11529 ,  H01L27/11519

    Abstract: An active resistor array of a semiconductor memory device comprises a first active resistor in a first active resistor region; a second active resistor in the first active resistor region and arranged in parallel with the first active resistor, and an isolation element layer interposed therebetween; a third active resistor formed in a second active resistor region; a first selection transistor formed in a first selection transistor region and connected to the second active resistor; and a second selection transistor formed in a second selection transistor region and connected to the third active resistor. The first and second selection transistors are connected to the same gate layer. The gate layer of the first and second selection transistors is on the isolation element layer. Since example embodiments may help to ensure the uniformity of the layout pattern, active resistance distribution may be improved due to reduction in process variation.

    CLOCK GATING CELL WITH LOW POWER AND INTEGRATED CIRCUIT INCLUDING THE SAME
    5.
    发明申请
    CLOCK GATING CELL WITH LOW POWER AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20210320660A1

    公开(公告)日：2021-10-14

    申请号：US17222197

    申请日：2021-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngo LEE ,  Ahreum KIM

    IPC: H03K19/00 ,  H03K3/012

    Abstract: In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.

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