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    VERTICAL SEMICONDUCTOR DEVICE
    1.
    发明申请
    VERTICAL SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220399273A1

    公开(公告)日：2022-12-15

    申请号：US17721481

    申请日：2022-04-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyeon YU ,  Pansuk KWAK ,  Daeseok BYEON

    IPC: H01L23/528 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11573

    Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

    MEMORY DEVICE FOR COLUMN REPAIR
    2.
    发明申请
    MEMORY DEVICE FOR COLUMN REPAIR 有权

    公开(公告)号：US20220100622A1

    公开(公告)日：2022-03-31

    申请号：US17245568

    申请日：2021-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong PARK ,  Minsu KIM ,  Daeseok BYEON ,  Pansuk KWAK

    IPC: G06F11/20 ,  G11C16/04

    Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230041064A1

    公开(公告)日：2023-02-09

    申请号：US17709910

    申请日：2022-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyeon YU ,  Pansuk KWAK ,  Daeseok BYEON

    IPC: G11C16/04 ,  G11C16/08

    Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

    MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210043639A1

    公开(公告)日：2021-02-11

    申请号：US16814491

    申请日：2020-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

    IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L27/11582

    Abstract: A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction. Each of the first and second cell contact regions includes first pads having different lengths to each other in the first direction and second pads different from the first pads, and the cell contacts are connected to the wordlines in the first pads. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.

    VERTICAL CAPACITOR STRUCTURE AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME
    5.
    发明申请
    VERTICAL CAPACITOR STRUCTURE AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200321349A1

    公开(公告)日：2020-10-08

    申请号：US16662073

    申请日：2019-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong KWON ,  Chanho KIM ,  Daeseok BYEON ,  Pansuk KWAK ,  Chiweon YOON

    IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/94 ,  H01L29/78

    Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

    INTEGRATED CIRCUIT INCLUDING POWER GATING CIRCUIT
    9.
    发明申请
    INTEGRATED CIRCUIT INCLUDING POWER GATING CIRCUIT 有权

    公开(公告)号：US20230073878A1

    公开(公告)日：2023-03-09

    申请号：US17886194

    申请日：2022-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon YU ,  Pansuk KWAK ,  Daeseok BYEON

    IPC: H03K19/00 ,  H03K19/003 ,  G06F1/26 ,  H03K3/027 ,  H03K17/687

    Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

    MEMORY DEVICE HAVING PHYSICAL UNCLONABLE FUNCTION AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    10.
    发明申请
    MEMORY DEVICE HAVING PHYSICAL UNCLONABLE FUNCTION AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20220399056A1

    公开(公告)日：2022-12-15

    申请号：US17569786

    申请日：2022-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong PARK ,  Pansuk KWAK ,  Daeseok BYEON

    IPC: G11C13/00 ,  G11C5/06

    Abstract: Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

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