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    SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20250048631A1

    公开(公告)日：2025-02-06

    申请号：US18664690

    申请日：2024-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung Kim ,  Junhyoung Kim ,  Joonyoung Kwon ,  Siwan Kim ,  Sukkang Sung

    IPC: H10B43/27 ,  H10B43/40

    Abstract: A semiconductor memory device including a cell array structure and a peripheral circuit structure is provided. The cell array structure includes a first stack structure, a second stack structure on the first stack structure, and a third stack structure on the second stack structure, each of the first to third stack structures including a plurality of word lines, vertical channel structures extending into the first to third stack structures, and a second cell contact plug extending into the first to third stack structures and connected to a second contact plug at an end of a second word line in the second stack structure. The second cell contact plug includes a first horizontal protrusion having a horizontal width that increases discontinuously at a connection portion of the first stack structure and the second stack structure.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    2.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210242236A1

    公开(公告)日：2021-08-05

    申请号：US17036997

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/522

    Abstract: A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

    Semiconductor device including stack structure with flat region
    4.
    发明授权
    Semiconductor device including stack structure with flat region 有权

    公开(公告)号：US11616021B2

    公开(公告)日：2023-03-28

    申请号：US17021321

    申请日：2020-09-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11582

    Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

    Electronic device with improved visibility of user interface
    7.
    发明授权
    Electronic device with improved visibility of user interface 有权

    公开(公告)号：US11211029B2

    公开(公告)日：2021-12-28

    申请号：US17023752

    申请日：2020-09-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyeong Cheon ,  Minkyu Park ,  Daewon Kim ,  Siwan Kim ,  Ukhyun Kim ,  Junho Lee ,  Eunsil Lim ,  Jungwoo Choi

    IPC: G09G5/00 ,  G09G5/02 ,  G06T7/90 ,  G09G5/37 ,  G06F3/0482

    Abstract: An electronic device and method are disclosed herein. The electronic device includes a display, and a processor. The processor implements the method, including: acquiring a background image of a screen generated for display, a region of interest (ROI) where a user interface (UI) element is to be displayed, calculating a value indicating a shape complexity of the ROI, dividing the ROI into a plurality of clusters according to designated attributes, calculating difference values indicating a contrast between each of the plurality of clusters and the UI element, identifying a minimum difference value from among the difference values as a contrast difference value, calculating a result value indicating a degree of visibility of the UI element relative to the background image, determining an image effect to be applied to the UI element, based on the result value, and display to the altered ROI the UI element.

    Three-dimensional semiconductor memory devices
    8.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US11917822B2

    公开(公告)日：2024-02-27

    申请号：US17036997

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    Abstract: A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

    Three-dimensional semiconductor memory device
    9.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11839091B2

    公开(公告)日：2023-12-05

    申请号：US17011156

    申请日：2020-09-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Bonghyun Choi ,  Siwan Kim

    IPC: H10B43/20 ,  H10B69/00

    CPC classification number: H10B69/00 ,  H10B43/20

    Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

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