公开(公告)号：US20240357819A1

公开(公告)日：2024-10-24

申请号：US18761012

申请日：2024-07-01

Applicant: Lodestar Licensing Group LLC

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L28/00 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20240224516A1

公开(公告)日：2024-07-04

申请号：US18439662

申请日：2024-02-12

Applicant: Lodestar Licensing Group LLC

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H10B41/35 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/786 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/76877 ,  H01L21/823412 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/24 ,  H01L29/78621 ,  H01L29/78681 ,  H01L29/78696 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US12029039B2

公开(公告)日：2024-07-02

申请号：US18096341

申请日：2023-01-12

Applicant: Lodestar Licensing Group LLC

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H10B43/27 ,  H01L23/522 ,  H01L49/02 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L28/00 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US12200938B2

公开(公告)日：2025-01-14

申请号：US18497790

申请日：2023-10-30

Applicant: Lodestar Licensing Group LLC

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/115 ,  G11C16/08 ,  H01L21/28 ,  H01L23/532 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US20240147729A1

公开(公告)日：2024-05-02

申请号：US18497790

申请日：2023-10-30

Applicant: Lodestar Licensing Group LLC

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H10B43/40 ,  G11C16/08 ,  H01L21/28 ,  H01L23/532 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C16/08 ,  H01L23/5329 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.