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公开(公告)号：US20230052161A1
公开(公告)日：2023-02-16
申请号：US17873739
申请日：2022-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyeong Seok , Younggul Song , Eunchu Oh , Byungchul Jang , Joonsung Lim
Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.
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公开(公告)号：US20240331782A1
公开(公告)日：2024-10-03
申请号：US18539914
申请日：2023-12-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyeong Seok , Beomkyu Shin , Eunchu Oh
CPC classification number: G11C16/3431 , G11C16/0483 , G11C16/16 , G11C16/3445 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B80/00 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A memory block is divided into sub blocks including a first sub block and a second sub block that are disposed in a vertical direction where the memory block includes a plurality of cell strings and each cell string includes a plurality of memory cells that are disposed in the vertical direction. A normal erase operation is performed independently with respect to each of the sub blocks. A disturbance verification read operation with respect to the first sub block is performed to determine whether a threshold voltage of memory cells connected to a wordline in an erased state of the first sub block is increased higher than a reference level. A post erase operation is selectively performed based on a result of the disturbance verification read operation to decrease the threshold voltage of memory cells in the erased state of the first sub block.
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公开(公告)号：US12033706B2
公开(公告)日：2024-07-09
申请号：US17873739
申请日：2022-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyeong Seok , Younggul Song , Eunchu Oh , Byungchul Jang , Joonsung Lim
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/16
Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.
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Patent Agency Ranking
4.发明授权公开(公告)号：US11537471B2
公开(公告)日：2022-12-27
申请号：US17469377
申请日：2021-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Eunchu Oh , Youngkwang Yoo , Younggeun Lee
Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
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5.发明授权公开(公告)号：US11507460B2
公开(公告)日：2022-11-22
申请号：US17448995
申请日：2021-09-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Eunchu Oh , Youngkwang Yoo , Younggeun Lee
Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
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公开(公告)号：US12154646B2
公开(公告)日：2024-11-26
申请号：US17816601
申请日：2022-08-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyeong Seok , Younggul Song , Eunchu Oh
Abstract: In a method of reprogramming data in a nonvolatile memory device including a plurality of pages each of which includes a plurality of memory cells, first page data programmed in a first page is read from among a plurality of page data programmed in the plurality of pages. The plurality of page data have a threshold voltage distribution including a plurality of states. An error correction code (ECC) decoding is performed on the first page data. A reprogram operation is selectively performed on target bits in which an error occurs among a plurality of bits included in the first page data based on a result of performing the ECC decoding on the first page data and a reprogram voltage. The target bits correspond to a first state among the plurality of states. A voltage level of the reprogram voltage is adaptively changed.
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7.发明授权公开(公告)号：US11847024B2
公开(公告)日：2023-12-19
申请号：US17972804
申请日：2022-10-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Eunchu Oh , Youngkwang Yoo , Younggeun Lee
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0679
Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
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8.发明授权公开(公告)号：US11144393B2
公开(公告)日：2021-10-12
申请号：US16840581
申请日：2020-04-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeongho Lee , Youngsik Kim , Seungyou Baek , Eunchu Oh , Youngkwang Yoo , Younggeun Lee
Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
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