-
公开(公告)号:US20230420429A1
公开(公告)日:2023-12-28
申请号:US17848448
申请日:2022-06-24
发明人: Sheng-Kai Chang , Leo Li , Chung-Hsien Hun , Lieh-Chuan Chen , Chien-Li Kuo
IPC分类号: H01L25/16 , H01L23/00 , H01L23/498 , H01L23/14 , H01L23/538 , H01L21/56 , H01L21/48
CPC分类号: H01L25/162 , H01L24/32 , H01L24/16 , H01L24/73 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/145 , H01L23/5381 , H01L23/5385 , H01L23/5386 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/4853 , H01L24/96 , H01L24/97 , H01L2224/16227 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/37001 , H01L2924/3511 , H01L2924/30205 , H01L23/49822 , H01L2924/182 , H01L2924/186
摘要: A semiconductor structure may include an interposer including on-interposer bump structures, at least one semiconductor die bonded to a first subset of the on-interposer bump structures through first solder material portions, at least one spacer die bonded to a second subset of the on-interposer bump structures through second solder material portions, and a molding compound die frame laterally surrounding each of the at least one semiconductor die and the at least one spacer die. Each of the at least one semiconductor die includes a respective set of transistors and a respective set of metal interconnect structures. Each of the at least one spacer die is free from any transistor therein.
-
公开(公告)号:US20240297087A1
公开(公告)日:2024-09-05
申请号:US18115840
申请日:2023-03-01
发明人: Sheng-Kai CHANG , Chih-Kang Han , Leo Li , Lieh-Chuan Chen , Chien-Li Kuo
IPC分类号: H01L23/16 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065
CPC分类号: H01L23/16 , H01L21/4853 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L21/563 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/96 , H01L24/97 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/96 , H01L2224/97 , H01L2924/1011
摘要: A package module includes an interposer, a plurality of semiconductor dies on the interposer, a module stiffener on the interposer adjacent to the plurality of semiconductor dies, and a molding material layer on the interposer around the plurality of semiconductor dies and the module stiffener.
-
3.
公开(公告)号:US20240332212A1
公开(公告)日:2024-10-03
申请号:US18191085
申请日:2023-03-28
发明人: Wen-Yi Lin , Yi-Che Chiang , Chien-Chen Li , Chien-Li Kuo , Kuo-Chio Liu
CPC分类号: H01L23/562 , H01L25/50 , H10B80/00 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
摘要: A package structure includes a package substrate, a semiconductor die module on the package substrate, a ring structure on the package substrate adjacent to the semiconductor die module, and a hybrid adhesive having a first modulus and a second modulus less than the first modulus and attaching the ring structure to the package substrate.
-
公开(公告)号:US12100754B2
公开(公告)日:2024-09-24
申请号:US17215268
申请日:2021-03-29
发明人: Chi-Fu Lin , Cheng-Hsin Chen , Ming-I Hsu , Kun-Ming Huang , Chien-Li Kuo
IPC分类号: H01L29/739 , H01L21/225 , H01L29/06 , H01L29/10 , H01L29/66
CPC分类号: H01L29/7394 , H01L21/225 , H01L29/0696 , H01L29/1095 , H01L29/66325
摘要: A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.
-
-
-