公开(公告)号：US12166076B2

公开(公告)日：2024-12-10

申请号：US17402930

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hong Chang ,  Yi-Hsiu Liu ,  You-Ting Lin ,  Chih-Chung Chang ,  Kuo-Yi Chao ,  Jiun-Ming Kuo ,  Yuan-Ching Peng ,  Sung-En Lin ,  Chia-Cheng Chao ,  Chung-Ting Ko

IPC: H01L33/62 ,  H01L21/768 ,  H01L25/075 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

公开(公告)号：US12080553B2

公开(公告)日：2024-09-03

申请号：US17353380

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/0338 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/66795

Abstract: Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.

公开(公告)号：US20240170341A1

公开(公告)日：2024-05-23

申请号：US18152390

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ming Chen ,  Tsung-Lin Lee ,  Chia-Ho Chu ,  Sung-En Lin ,  Sen-Hong Syue

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823857 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Semiconductor devices and methods of manufacture are discussed. In an embodiment, a method of manufacturing a semiconductor device includes: forming first nanostructures from a first material over a substrate; forming second nanostructures from a second material different from the first material over the substrate, wherein the first nanostructures and the second nanostructures alternate vertically above the substrate; removing the first nanostructures; after the removing the first nanostructures forming an interposer in between the second nanostructures; after the forming the interposer forming a first source/drain region over the substrate and in direct physical contact with the second nanostructures; and removing the interposer exposing surfaces of each of the second nanostructures.

公开(公告)号：US20240087947A1

公开(公告)日：2024-03-14

申请号：US18152477

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Yu-Cheng Shiau ,  Li-Jung Kuo ,  Sung-En Lin ,  Kuo-Chin Liu

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/762 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/31116 ,  H01L29/0684

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.

公开(公告)号：US10468409B2

公开(公告)日：2019-11-05

申请号：US15920967

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Lee ,  Jian-Shiou Huang ,  Chih-Tang Peng ,  Sung-En Lin

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/108

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure protruding from a semiconductor substrate. The fin structure includes a first portion and an overlying second portion. The first portion is formed of a material that is the same as that of the semiconductor substrate and different from that of the second portion. The semiconductor device structure also includes a liner structure and an isolation feature. The liner structure includes a carbon-doped silicon oxide film covering the semiconductor substrate and the first portion of the first fin structure and a nitrogen-containing film over the carbon-doped silicon oxide film. The isolation feature is over the nitrogen-containing film and surrounded by the liner structure.

公开(公告)号：US20190006227A1

公开(公告)日：2019-01-03

申请号：US15725996

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin TSAI ,  Shing-Chyang Pan ,  Sung-En Lin ,  Tze-Liang Lee ,  Jung-Hau Shiu ,  Jen Hung Wang

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02019 ,  H01L21/0337 ,  H01L2221/101

Abstract: The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases.

公开(公告)号：US20250056851A1

公开(公告)日：2025-02-13

申请号：US18928641

申请日：2024-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hong Chang ,  Yi-Hsiu Liu ,  You-Ting Lin ,  Chih-Chung Chang ,  Kuo-Yi Chao ,  Jiun-Ming Kuo ,  Yuan-Ching Peng ,  Sung-En Lin ,  Chia-Cheng Chao ,  Chung-Ting Ko

IPC: H01L29/06 ,  H01L21/768 ,  H01L29/786

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.

公开(公告)号：US20240379359A1

公开(公告)日：2024-11-14

申请号：US18782794

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yu Kao ,  Sung-En Lin ,  Chia-Cheng Chao

IPC: H01L21/033 ,  H01L21/308

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

公开(公告)号：US20240363349A1

公开(公告)日：2024-10-31

申请号：US18771311

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/0338 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/66795

Abstract: Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.

公开(公告)号：US12002719B2

公开(公告)日：2024-06-04

申请号：US18083757

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.