公开(公告)号：US20230352583A1

公开(公告)日：2023-11-02

申请号：US17661221

申请日：2022-04-28

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Ravi Pramod Kumar VEDULA ,  Hyunchul JUNG

IPC: H01L29/78 ,  H01L29/66 ,  H03F3/21

CPC classification number: H01L29/7835 ,  H01L29/66492 ,  H03F3/211 ,  H03F2200/294 ,  H03F2200/451

Abstract: Disclosed is a transistor of a device that has an asymmetric resistance or an asymmetric capacitive coupling or both. When used in a cascode configuration in an amplifier, low current performance of the amplifier is improved. Asymmetric resistance may be enabled through differentially doping source and drain structures of the transistor and/or through differentially manipulating geometries the source and drain structures. Asymmetric capacitive coupling may be enabled through providing dielectrics and differentially locating the dielectrics above a gate of the transistor. Further, a body of the transistor may be biased.

公开(公告)号：US20200185522A1

公开(公告)日：2020-06-11

申请号：US16788197

申请日：2020-02-11

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY ,  George Pete IMTHURN ,  Sinan GOKTEPELI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L21/762 ,  H01L21/28

Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.

公开(公告)号：US20190109570A1

公开(公告)日：2019-04-11

申请号：US15959562

申请日：2018-04-23

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Sinan GOKTEPELI ,  George Pete IMTHURN

IPC: H03F3/195 ,  H01L23/66 ,  H03F1/26 ,  H03F3/193 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092

Abstract: A radio frequency integrated circuit (RFIC) includes multi-finger transistors including discrete diffusion regions and interconnected within a reconfigured form factor as a single switch transistor. The RFIC also includes a source bus having a first plurality of source fingers coupled to each source region of the multi-finger transistors and a second plurality of source fingers orthogonally coupled to the first plurality of source fingers. The second plurality of source fingers couple the discrete diffusion regions in parallel. The RFIC also includes a drain bus having a first plurality of drain fingers coupled to each drain region of the multi-finger transistors and a second plurality of drain fingers orthogonally coupled to the first plurality of drain fingers. The second plurality of drain fingers electrically couple the discrete diffusion regions in parallel. The RFIC further includes a plurality of interconnected body contacts to bias a body of each of the multi-finger transistors.

公开(公告)号：US20220109441A1

公开(公告)日：2022-04-07

申请号：US17061314

申请日：2020-10-01

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY

IPC: H03K17/687 ,  H01L27/06 ,  H01L21/8234

Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a field effect transistor (FET). The FET has a ferroelectric gate stack having a source region, a drain region, a body region, and a gate. The RFIC also includes a first resistor coupled between a first bias supply and the body region. The RFIC further includes a second resistor coupled between the gate and a second bias supply.

公开(公告)号：US20210351811A1

公开(公告)日：2021-11-11

申请号：US17150610

申请日：2021-01-15

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  George Pete IMTHURN ,  Anton ARRIAGADA ,  Sinan GOKTEPELI

IPC: H04B1/44 ,  H03K17/687

Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

公开(公告)号：US20210280452A1

公开(公告)日：2021-09-09

申请号：US16809796

申请日：2020-03-05

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Stephen Alan FANELLI

IPC: H01L21/762

Abstract: Utilizing crystal orientation channeling through the semiconductor lattice structure of a silicon-on-insulator (SOI) wafer to create a thermally stable implanted amorphous layer beneath a buried oxide (BOX) layer in the SOI wafer is described. Utilizing channeling in this manner may involve tilting and/or twisting the SOI wafer to align axes of the crystal orientation channels with projections vectors from an implanter. One example method of fabricating a semiconductor device generally includes orienting an SOI substrate, the SOI substrate having a BOX layer and a device layer disposed above the BOX layer, such that directions of projection vectors from an implanter are substantially aligned with longitudinal axes of crystal orientation channels in a lattice structure of a semiconductor material of the device layer; and projecting, with the implanter, ions or particles into the crystal orientation channels of the oriented SOI substrate to create an implanted layer below the BOX layer.

公开(公告)号：US20240321729A1

公开(公告)日：2024-09-26

申请号：US18186781

申请日：2023-03-20

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Ravi Pramod Kumar VEDULA ,  Yufei WU

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Disclosed is an integrated circuit (IC) with an inductor formed from redistribution layers (RDLs). An airgap is provided in an interlayer dielectric (ILD) under the bottom most RDL that makes up the inductor. In this way, an inductor with high Q value is achieved. Also, inductor isolation is improved. Thus, circuits may be placed under the inductor resulting is a smaller die.

公开(公告)号：US20230092546A1

公开(公告)日：2023-03-23

申请号：US17481618

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Vikram SEKAR

IPC: H01L27/12 ,  H01L23/535

Abstract: A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.

公开(公告)号：US20210242127A1

公开(公告)日：2021-08-05

申请号：US16779192

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Farid AZZAZY ,  Ravi Pramod Kumar VEDULA

IPC: H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) is described. The IC includes a substrate and a plurality of back-end-of-line (BEOL) layers on the substrate. The IC also includes a trench having tapered sidewalls and a base in a BEOL layer of the plurality of BEOL layers on the substrate. The IC further includes a metal-insulator-metal (MIM) capacitor on the tapered sidewalls and the base of the trench in the BEOL layer. The MIM capacitor includes a first conductive layer to line the tapered sidewalls and the base of the trench. The MIM capacitor also includes a dielectric layer to line the first conductive layer on the tapered sidewalls and the base of the trench. The MIM capacitor further includes a second conductive layer on the dielectric layer and filling the trench in the BEOL layer.

公开(公告)号：US20190109152A1

公开(公告)日：2019-04-11

申请号：US16000501

申请日：2018-06-05

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Sinan GOKTEPELI ,  Jarred MOORE

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/66

Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET), including a source region, a drain region, a body region, and a gate. The RFIC also includes a body bypass resistor coupled between the gate and the body region. The RFIC further includes a gate isolation resistor coupled between the gate and the body region. The RFIC also includes a diode coupled between the body bypass resistor and the gate isolation resistor.