公开(公告)号：US20240096750A1

公开(公告)日：2024-03-21

申请号：US17933187

申请日：2022-09-19

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Stanley Seungchul SONG

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5283 ,  H01L27/1203 ,  H01L29/41725

Abstract: Disclosed are integrated circuit structures with through-substrate vias (TSVs) processed through self-aligned contact modules. As a result, much smaller and/or denser TSVs are formed with low mechanical stress. The denser TSVs allow for more flexible wiring options.

公开(公告)号：US20190386121A1

公开(公告)日：2019-12-19

申请号：US16011430

申请日：2018-06-18

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Stephen Alan FANELLI

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.

公开(公告)号：US20240105797A1

公开(公告)日：2024-03-28

申请号：US17934400

申请日：2022-09-22

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.

公开(公告)号：US20190198461A1

公开(公告)日：2019-06-27

申请号：US15947416

申请日：2018-04-06

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Sinan GOKTEPELI ,  George Pete IMTHURN

IPC: H01L23/66 ,  H01L21/268 ,  B23K26/362 ,  H01L23/544 ,  H03H9/64 ,  H03H9/02

CPC classification number: H01L23/66 ,  B23K26/362 ,  H01L21/268 ,  H01L23/544 ,  H01L2223/6677 ,  H03H9/02566 ,  H03H9/02574 ,  H03H9/02622 ,  H03H9/64

Abstract: A method of constructing a layer transferred radio frequency (RF) filter-on-insulator wafer includes exposing a front-side of a bulk RF wafer to a laser light source to form a modified layer at a predetermined depth along a horizontal length of the bulk RF wafer. The method also includes bonding the front-side of the bulk RF wafer to a front-side of a semiconductor handle wafer through an insulator layer. The method further includes forming an RF filter layer from the bulk RF wafer. The method also includes selectively etching away the modified layer from the RF filter layer to the predetermined depth to complete the layer transferred RF filter-on-insulator wafer.

公开(公告)号：US20190103339A1

公开(公告)日：2019-04-04

申请号：US15975434

申请日：2018-05-09

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Stephen Alan FANELLI

IPC: H01L23/48 ,  H01L25/11 ,  H01L25/065 ,  H01L21/768 ,  H01L21/8234 ,  H01L49/02

Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC also includes a contact layer on the second-side of the bulk semiconductor die. The RFIC further includes a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.

公开(公告)号：US20210351811A1

公开(公告)日：2021-11-11

申请号：US17150610

申请日：2021-01-15

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  George Pete IMTHURN ,  Anton ARRIAGADA ,  Sinan GOKTEPELI

IPC: H04B1/44 ,  H03K17/687

Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

公开(公告)号：US20210257488A1

公开(公告)日：2021-08-19

申请号：US16792384

申请日：2020-02-17

Applicant: QUALCOMM Incorporated

Inventor： Jean RICHAUD ,  George Pete IMTHURN

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to electrically erasable programmable read-only memory (EEPROM) device comprising at least one EEPROM cell structure. The EEPROM device generally includes a first active region, a second active region, a channel region disposed between the first active region and the second active region, a floating gate structure disposed above the channel region and separated from the channel region by a first dielectric layer, a control gate structure disposed above the floating gate structure and separated from the floating gate structure by a second dielectric layer, and a bottom gate structure disposed below the channel region.

公开(公告)号：US20190109232A1

公开(公告)日：2019-04-11

申请号：US16152105

申请日：2018-10-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Sivakumar KUMARASAMY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/40

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

公开(公告)号：US20240154406A1

公开(公告)日：2024-05-09

申请号：US17983261

申请日：2022-11-08

Applicant: QUALCOMM Incorporated

Inventor： George Pete IMTHURN ,  Woojin CHOI ,  Maurice Adrianus DE JONGH ,  Jeffrey Donald MILLER ,  Qingqing LIANG

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: A radio frequency (RF) device is described. The RF device includes a first RF switch coupled in series to a first RF port and coupled in parallel to an RF common (RFC) port. The RF device also includes an electrostatic discharge (ESD) dissipation switch coupled to the RF common port. The ESD dissipation switch includes a switch field effect transistor (FET). The switch FET includes a gate on an active layer of a substrate, and a symmetric silicide area block (SAB) on a first sidewall spacer and a second sidewall spacer, opposite the first sidewall spacer, and on a gate surface of the gate, opposite the active layer of the substrate.

公开(公告)号：US20230282716A1

公开(公告)日：2023-09-07

申请号：US17653481

申请日：2022-03-04

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  George Pete IMTHURN ,  Yun Han CHU ,  Sivakumar KUMARASAMY

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/401 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7841

Abstract: Disclosed is a transistor of a device that has double side contacts in which at least a drain contact is on the opposite side of the gate. In this way, gate resistance can be reduced without increasing parasitic capacitances between gate and drain.