公开(公告)号：US20250087640A1

公开(公告)日：2025-03-13

申请号：US18465900

申请日：2023-09-12

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

Abstract: Disclosed are packages that may include first and second substrates with first and second chips therebetween. The first chip may be a logic chip and the second chip may be a processing near memory (PNM) chip. The active side of the first chip may face the first substrate and the active side of the second chip may face the second substrate. The first chip may be encapsulated by a first mold, and the second chip may be encapsulated by a second mold. The first and/or the second molds may be thermally conductive. A third chip (e.g., a memory) may be on the second substrate opposite the second chip. The second substrate may include very short vertical connections that connect the active sides of the second and third chips.

公开(公告)号：US20220148953A1

公开(公告)日：2022-05-12

申请号：US17093090

申请日：2020-11-09

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L23/498 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A reconstituted substrate, a packaged assembly comprising a reconstituted substrate, and methods for fabricating a reconstituted substrate. An example reconstituted substrate generally includes multiple package-level substrates implemented with different substrate technologies and held together. An example method for fabricating a reconstituted substrate generally includes forming multiple package-level substrates implemented with different substrate technologies, arranging the multiple package-level substrates, and adding a material to hold the multiple package-level substrates together.

公开(公告)号：US20210343684A1

公开(公告)日：2021-11-04

申请号：US16864363

申请日：2020-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L25/16 ,  H05K1/18 ,  H01L23/498 ,  H01L23/00 ,  H01L49/02 ,  H01L21/48

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.

公开(公告)号：US20190157160A1

公开(公告)日：2019-05-23

申请号：US15817452

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Cimang LU ,  Stanley Seungchul SONG ,  Periannan CHIDAMBARAM

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/308

Abstract: Aspects of the disclosure are directed to a semiconductor device. The semiconductor device may include a plurality of fins formed on a semiconductor substrate including a bulk semiconductor material, a plurality of shallow trench isolation (STI) trenches formed between the plurality of fins, a hardmask formed around the plurality of fins, and a plurality of fin bottom portions formed below the plurality of fins.

公开(公告)号：US20240096750A1

公开(公告)日：2024-03-21

申请号：US17933187

申请日：2022-09-19

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Stanley Seungchul SONG

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5283 ,  H01L27/1203 ,  H01L29/41725

Abstract: Disclosed are integrated circuit structures with through-substrate vias (TSVs) processed through self-aligned contact modules. As a result, much smaller and/or denser TSVs are formed with low mechanical stress. The denser TSVs allow for more flexible wiring options.

公开(公告)号：US20220108968A1

公开(公告)日：2022-04-07

申请号：US17061737

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM ,  Abdolreza LANGARI

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC: H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20220013444A1

公开(公告)日：2022-01-13

申请号：US16927823

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H01L23/498 ,  H03F3/213

Abstract: A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

公开(公告)号：US20210281234A1

公开(公告)日：2021-09-09

申请号：US16812294

申请日：2020-03-07

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H7/01 ,  H01L49/02 ,  H01F17/00 ,  H01L27/06

Abstract: An improved filter for high frequency, such as 5G wireless communication, may include inductor-Q improvement and reduced die-size with a hybrid 3D-inductor integration. In some examples, the inductors may be formed using an IPD and a fan-out package. For instance, a first multilayer substrate comprises a plurality of metal insulator metal (MIM) capacitors formed using various layers (e.g., M1 and M2) and a first portion of the 3D inductors, and a second multilayer substrate comprises at least a second portion of the 3D inductors. The 3D inductors may be electrically coupled to the MIM capacitors to form at least one filter network.

公开(公告)号：US20210234526A1

公开(公告)日：2021-07-29

申请号：US16750625

申请日：2020-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H7/38 ,  H01Q1/22 ,  H01Q1/52 ,  H04B1/40

Abstract: Impedance matching transceivers may include a tuning circuit to match the transceiver module impedance to the housing conditions. In some examples, the impedance matching is controlled by tuning-circuits that may be integrated into a transceiver module by using a fan-out package (FO PKG). One example of a tuning circuit may include a switch to isolate the parallel capacitors, such that when the switch is on or closed the parallel capacitors are active.