公开(公告)号：US20210280571A1

公开(公告)日：2021-09-09

申请号：US16808336

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Bharani CHAVA ,  Foua VANG ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H01L27/02 ,  H01L23/528 ,  H03K19/0185

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P

公开(公告)号：US20240055356A1

公开(公告)日：2024-02-15

申请号：US18492402

申请日：2023-10-23

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; a first bridge coupled to the first integrated device and the second integrated device through at least a third plurality of solder interconnects, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device, through at least the third plurality of solder interconnects; and a second bridge coupled to the first integrated device and the second integrated device through a fourth plurality of solder interconnects.

公开(公告)号：US20220415808A1

公开(公告)日：2022-12-29

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US20220415868A1

公开(公告)日：2022-12-29

申请号：US17358838

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Abinash ROY ,  Lohith Kumar VEMULA ,  Bharani CHAVA ,  Jonghae KIM

IPC: H01L25/16 ,  H01L23/13 ,  H01L21/48 ,  H01L23/498 ,  H01L23/64

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.

公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC: H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20220077109A1

公开(公告)日：2022-03-10

申请号：US17015308

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Stanley Seungchul SONG ,  Abinash ROY ,  Jonghae KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：US20230387077A1

公开(公告)日：2023-11-30

申请号：US18365063

申请日：2023-08-03

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H03K17/687

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/58 ,  H01L24/16 ,  H03K17/6871 ,  H01L2224/16227

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The first power interconnect includes a first power plane. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The second power interconnect includes a second power plane. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US20220246580A1

公开(公告)日：2022-08-04

申请号：US17162621

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31 ,  H03K17/687

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US20220026474A1

公开(公告)日：2022-01-27

申请号：US16935092

申请日：2020-07-21

Applicant: QUALCOMM Incorporated

Inventor： Stefano FACCHIN ,  Baptiste GRAVE ,  Bharani CHAVA ,  David Jonathan WALSHE

IPC: G01R19/165 ,  H01L23/528 ,  H01L27/092 ,  H01L29/24 ,  H01L29/786

Abstract: An IC is provided. The IC includes a power grid including Mx layer interconnects extending in a first direction on an Mx layer and Mx+1 layer interconnects extending in a second direction orthogonal to the first direction on an Mx+1 layer, where x>5. In addition, the IC includes a plurality of power switches. Further, the IC includes at least one sensing element located between the Mx layer and the Mx+1 layer and configured to measure a voltage drop to devices powered by the plurality of power switches. The one or more of the plurality of power switches may be located below the power grid. The power switches of the plurality of power switches may be adjacent in the first direction and in the second direction to each sensing element of the at least one sensing element.

公开(公告)号：US20210408015A1

公开(公告)日：2021-12-30

申请号：US16917212

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Abinash ROY ,  Bharani CHAVA

IPC: H01L27/112 ,  H01L23/538 ,  H01L21/48

Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.