公开(公告)号：US20190273116A1

公开(公告)日：2019-09-05

申请号：US16116744

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Stephen Alan FANELLI ,  Yun Han CHU

IPC: H01L27/20 ,  H03H9/05 ,  H03H9/56 ,  H03H9/64 ,  H03H3/02 ,  H03H3/08

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

公开(公告)号：US20200075633A1

公开(公告)日：2020-03-05

申请号：US16115352

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Stephen Alan FANELLI ,  Sinan GOKTEPELI

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06

Abstract: An integrated circuit device includes a portion of a support wafer (e.g., a handle wafer), silicon on insulator layer, a first active device, and a second active device. The first active device has a first semiconductor thickness in a dielectric layer (e.g., a buried oxide layer). The first active device is on the SOI layer. The second active device has a second semiconductor thickness in the same dielectric layer as the first active device. The supporting wafer supports the first active device and the second active device. The second active device is also on the SOI layer. The first and second thicknesses are different from one another.

公开(公告)号：US20190386121A1

公开(公告)日：2019-12-19

申请号：US16011430

申请日：2018-06-18

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Stephen Alan FANELLI

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.

公开(公告)号：US20180301419A1

公开(公告)日：2018-10-18

申请号：US15658296

申请日：2017-07-24

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306

Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.

公开(公告)号：US20210280452A1

公开(公告)日：2021-09-09

申请号：US16809796

申请日：2020-03-05

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Stephen Alan FANELLI

IPC: H01L21/762

Abstract: Utilizing crystal orientation channeling through the semiconductor lattice structure of a silicon-on-insulator (SOI) wafer to create a thermally stable implanted amorphous layer beneath a buried oxide (BOX) layer in the SOI wafer is described. Utilizing channeling in this manner may involve tilting and/or twisting the SOI wafer to align axes of the crystal orientation channels with projections vectors from an implanter. One example method of fabricating a semiconductor device generally includes orienting an SOI substrate, the SOI substrate having a BOX layer and a device layer disposed above the BOX layer, such that directions of projection vectors from an implanter are substantially aligned with longitudinal axes of crystal orientation channels in a lattice structure of a semiconductor material of the device layer; and projecting, with the implanter, ions or particles into the crystal orientation channels of the oriented SOI substrate to create an implanted layer below the BOX layer.

公开(公告)号：US20190131454A1

公开(公告)日：2019-05-02

申请号：US15800916

申请日：2017-11-01

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. A strain inducing intermediate layer (SIIL) is on the porous silicon layer. A silicon layer is on the SIIL. Lattice constant of the silicon layer is different from lattice constant of the SIIL. Thus, the silicon layer is strained. By employing different strain inducing materials in the SIIL, the silicon layer can be used to form different complementary metal oxide semiconductor (CMOS) transistors with improved characteristics.

公开(公告)号：US20180277632A1

公开(公告)日：2018-09-27

申请号：US15669704

申请日：2017-08-04

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/10 ,  H01L21/683 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L21/20 ,  H01L21/306 ,  H01L23/528 ,  H01L23/00 ,  H01L29/78

Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

公开(公告)号：US20210098600A1

公开(公告)日：2021-04-01

申请号：US16589444

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

公开(公告)号：US20200044621A1

公开(公告)日：2020-02-06

申请号：US16050212

申请日：2018-07-31

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Sinan GOKTEPELI ,  Alexandre Augusto SHIRAKAWA

IPC: H03H3/10 ,  H03H9/02 ,  H01L41/312 ,  H01L41/338

Abstract: In certain aspects, a thin film surface acoustic wave (SAW) die comprises a high-resistivity substrate, a bonding layer on the high-resistivity substrate, and a thin film piezoelectric island on the bonding layer, where an edge of the thin film piezoelectric island is offset from an edge of the bonding layer.

公开(公告)号：US20190198461A1

公开(公告)日：2019-06-27

申请号：US15947416

申请日：2018-04-06

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Sinan GOKTEPELI ,  George Pete IMTHURN

IPC: H01L23/66 ,  H01L21/268 ,  B23K26/362 ,  H01L23/544 ,  H03H9/64 ,  H03H9/02

CPC classification number: H01L23/66 ,  B23K26/362 ,  H01L21/268 ,  H01L23/544 ,  H01L2223/6677 ,  H03H9/02566 ,  H03H9/02574 ,  H03H9/02622 ,  H03H9/64

Abstract: A method of constructing a layer transferred radio frequency (RF) filter-on-insulator wafer includes exposing a front-side of a bulk RF wafer to a laser light source to form a modified layer at a predetermined depth along a horizontal length of the bulk RF wafer. The method also includes bonding the front-side of the bulk RF wafer to a front-side of a semiconductor handle wafer through an insulator layer. The method further includes forming an RF filter layer from the bulk RF wafer. The method also includes selectively etching away the modified layer from the RF filter layer to the predetermined depth to complete the layer transferred RF filter-on-insulator wafer.