公开(公告)号：US20230197554A1

公开(公告)日：2023-06-22

申请号：US17558508

申请日：2021-12-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L23/3677 ,  H01L25/0655 ,  H01L21/4871 ,  H01L25/50

Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.

公开(公告)号：US20240096817A1

公开(公告)日：2024-03-21

申请号：US17932788

申请日：2022-09-16

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/02 ,  H01Q1/22 ,  H01Q3/36 ,  H01Q9/04 ,  H01Q21/06

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L23/3736 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/66 ,  H01L24/08 ,  H01Q1/02 ,  H01Q1/2283 ,  H01Q3/36 ,  H01Q9/0414 ,  H01Q21/065 ,  H01L23/49816 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/08225 ,  H01L2924/14215 ,  H01L2924/3025 ,  H01L2924/351

Abstract: Disclosed are techniques for on-chip electromagnetic interference (EMI) shielding. In an aspect, an integrated circuit includes a noise-sensitive device, a first metallization layer disposed on a first side of the noise-sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield around the first side of the noise-sensitive device, and a second metallization layer disposed on a second side of the noise-sensitive device opposite the first side of the noise-sensitive device, wherein the second metallization layer includes one or more conductive routing layers, and wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield around the second side of the noise-sensitive device.

公开(公告)号：US20220302107A1

公开(公告)日：2022-09-22

申请号：US17206950

申请日：2021-03-19

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/16 ,  H01L29/04 ,  H01L29/778 ,  H01L23/66 ,  H01L29/66 ,  H01L21/8258

Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor substrate. The RFIC also includes a compound semiconductor field effect transistor (FET). The compound semiconductor FET is composed of a gallium nitride (GaN) epitaxial stack in a trench in the bulk semiconductor substrate having sidewall spacers. The sidewall spacers are between the GaN epitaxial stack and sidewalls of the trench. A carbonized surface layer is at a base of the trench and coupled to the GaN epitaxial stack. The RFIC further includes a complementary metal oxide semiconductor (CMOS) transistor integrated with the compound semiconductor FET on the bulk semiconductor substrate.

公开(公告)号：US20210391234A1

公开(公告)日：2021-12-16

申请号：US16898096

申请日：2020-06-10

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

Abstract: A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.

公开(公告)号：US20200381398A1

公开(公告)日：2020-12-03

申请号：US16600300

申请日：2019-10-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

Abstract: 3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

公开(公告)号：US20200350431A1

公开(公告)日：2020-11-05

申请号：US16401189

申请日：2019-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: Certain aspects of the present disclosure generally relate to a transistor having a self-aligned drift region and asymmetric spacers. One example transistor generally includes a channel region; a gate region disposed above the channel region; a first implant region; a second implant region having a same doping type as the first implant region, but a different doping type than the channel region; a first spacer disposed adjacent to a first side of the gate region; a second spacer disposed adjacent to a second side of the gate region and having a wider width than the first spacer; and a drift region having an edge vertically aligned with an edge of the second spacer and disposed between the channel region and the second implant region. The channel region may be disposed between the first implant region and the drift region.

公开(公告)号：US20200350425A1

公开(公告)日：2020-11-05

申请号：US16401240

申请日：2019-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L29/778 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor device having heterogeneous transistors integrated on a diamond substrate. An example semiconductor device generally includes a diamond substrate, a first transistor disposed above the diamond substrate, the first transistor comprising gallium nitride, and a second transistor disposed above the diamond substrate, the second transistor comprising a different semiconductor than the first transistor.

公开(公告)号：US20200266290A1

公开(公告)日：2020-08-20

申请号：US16276762

申请日：2019-02-15

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/205 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region and a collector region. The collector region may include a proton implant region having an edge aligned with an edge of the emitter region. In certain aspects, the HBT device also includes a base region disposed between the emitter region and the collector region.

公开(公告)号：US20240203895A1

公开(公告)日：2024-06-20

申请号：US18067565

申请日：2022-12-16

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Jonghae KIM ,  Ranadeep DUTTA

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/566 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/14215 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/2027 ,  H01L2924/3025

Abstract: Disclosed are examples of multi-die modules that includes a die (e.g., a power amplifier) and an adjacent die placed side-by-side and bonded onto a substrate with a mold compound. The die (e.g., a switch or a low noise amplifier) may be double EMI shielded to minimize or even eliminate EMI/noise coupling with the adjacent die (e.g., switch, low noise amplifier, etc.). Another mold compound, which can be thermally conductive, may be provided to improve transfer of heat away from the die and/or the adjacent die.

公开(公告)号：US20230187106A1

公开(公告)日：2023-06-15

申请号：US17643685

申请日：2021-12-10

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Sang-June PARK ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H01C7/00

CPC classification number: H01C7/006

Abstract: Disclosed is a sheet resistor designed to operate in a high frequency environment. Unlike conventional sheet resistors, the equivalent series inductance (ESL) is minimized or even eliminated altogether when using the designed sheet resistor. As a result, better signal isolation can be achieved.