公开(公告)号：US20220109441A1

公开(公告)日：2022-04-07

申请号：US17061314

申请日：2020-10-01

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY

IPC: H03K17/687 ,  H01L27/06 ,  H01L21/8234

Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a field effect transistor (FET). The FET has a ferroelectric gate stack having a source region, a drain region, a body region, and a gate. The RFIC also includes a first resistor coupled between a first bias supply and the body region. The RFIC further includes a second resistor coupled between the gate and a second bias supply.

公开(公告)号：US20190109232A1

公开(公告)日：2019-04-11

申请号：US16152105

申请日：2018-10-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Sivakumar KUMARASAMY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/40

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

公开(公告)号：US20230282716A1

公开(公告)日：2023-09-07

申请号：US17653481

申请日：2022-03-04

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  George Pete IMTHURN ,  Yun Han CHU ,  Sivakumar KUMARASAMY

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/401 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7841

Abstract: Disclosed is a transistor of a device that has double side contacts in which at least a drain contact is on the opposite side of the gate. In this way, gate resistance can be reduced without increasing parasitic capacitances between gate and drain.

公开(公告)号：US20200373315A1

公开(公告)日：2020-11-26

申请号：US16419606

申请日：2019-05-22

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  George Pete IMTHURN ,  Sinan GOKTEPELI ,  Sivakumar KUMARASAMY

IPC: H01L27/11521 ,  H01L29/788 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L29/66

Abstract: Certain aspects of the present disclosure are generally directed to non-volatile memory (NVM) and techniques for operating and fabricating NVM. Certain aspects provide a memory cell for implementing NVM. The memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions. The memory cell also includes a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region, a first front gate region disposed adjacent to the second semiconductor region, and a first floating front gate region disposed adjacent to the third semiconductor region. In certain aspects, the memory cell includes a back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region.

公开(公告)号：US20190393340A1

公开(公告)日：2019-12-26

申请号：US16156729

申请日：2018-10-10

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY ,  George Pete IMTHURN ,  Sinan GOKTEPELI

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L21/28

Abstract: An integrated circuit is described. The integrated circuit includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET is on a first surface of an insulator layer of the integrated circuit. The MOSFET including a source region, a drain region, and a front gate. The MOSFET also includes an extended drain region between the drain region and a well proximate the front gate. The integrated circuit also includes back gates on a second surface opposite the first surface of the insulator layer. The back gates are overlapped by the extended drain region.

公开(公告)号：US20250015047A1

公开(公告)日：2025-01-09

申请号：US18348777

申请日：2023-07-07

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Jihong CHOI ,  Giridhar NALLAPATI ,  Sivakumar KUMARASAMY ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

Abstract: An integrated circuit (IC) is described. The IC includes a first die having a first semiconductor layer, a first active device layer and a first back-end-of-line (BEOL) layer. The IC also includes a second die having a second semiconductor layer, a second active device layer and a second back-end-of-line (BEOL) layer, and on the first die. The IC further includes a through substrate via (TSV) extending through the first die and the second die.

公开(公告)号：US20210242322A1

公开(公告)日：2021-08-05

申请号：US16778546

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Sivakumar KUMARASAMY ,  George Pete IMTHURN ,  Sinan GOKTEPELI

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/40

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.

公开(公告)号：US20200235107A1

公开(公告)日：2020-07-23

申请号：US16742886

申请日：2020-01-14

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Sivakumar KUMARASAMY

IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18

Abstract: Antifuse memory cells as well as other applications may provide advantages of conventional approaches. In some examples, a metal backside gate or contact may be formed in the insulator layer opposite the front side contacts and circuits. The metal backside gate or contact may allow a higher voltage on a low resistance and capacitance lie to be applied directly to the dielectric layer of the antifuse to more quickly breakdown the dielectric and program the antifuse.

公开(公告)号：US20200185522A1

公开(公告)日：2020-06-11

申请号：US16788197

申请日：2020-02-11

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY ,  George Pete IMTHURN ,  Sinan GOKTEPELI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L21/762 ,  H01L21/28

Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.