-
公开(公告)号：US20240022221A1
公开(公告)日：2024-01-18
申请号：US18319227
申请日：2023-05-17
Applicant: QUALCOMM Incorporated
Inventor： Zaid ABOUSH , Noshir Behli DUBASH , Abhijeet PAUL , Peter Graeme CLARKE
CPC classification number: H03F3/245 , H03F1/223 , H03F1/0277 , H03F2200/451 , H03F2200/294
Abstract: Devices and techniques for amplifying a signal are disclosed. For instance, an amplifier includes an input node and an output node; a first gain segment including: a first transistor, where a gate of the first transistor is coupled to the input node, a first terminal of the first transistor is coupled to a ground, and a second terminal of the first transistor is coupled to the output node; a second gain segment including: a second transistor, where a gate of the second transistor is coupled to the input node, a first terminal of the second transistor is coupled to the ground, and a second terminal of the second transistor is coupled to the output node, where the first gain segment and the second gain segment are arranged in parallel with respect to the output node; and a bias circuit.
-
公开(公告)号：US20210327826A1
公开(公告)日：2021-10-21
申请号：US17002643
申请日：2020-08-25
Applicant: QUALCOMM Incorporated
Inventor： Abhijeet PAUL , Mishel MATLOUBIAN
Abstract: An integrated device that includes a substrate, a circuit region located over the substrate, a design keep out region located over the substrate, and a periphery structure located over the substrate. The design keep out region laterally surrounds the circuit region. The periphery structure includes a first plurality of interconnects that laterally surrounds the design keep out region. The periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop.
-
公开(公告)号：US20240321729A1
公开(公告)日：2024-09-26
申请号：US18186781
申请日：2023-03-20
Applicant: QUALCOMM Incorporated
Inventor： Abhijeet PAUL , Ravi Pramod Kumar VEDULA , Yufei WU
IPC: H01L23/522
CPC classification number: H01L23/5227 , H01L28/10
Abstract: Disclosed is an integrated circuit (IC) with an inductor formed from redistribution layers (RDLs). An airgap is provided in an interlayer dielectric (ILD) under the bottom most RDL that makes up the inductor. In this way, an inductor with high Q value is achieved. Also, inductor isolation is improved. Thus, circuits may be placed under the inductor resulting is a smaller die.
-
公开(公告)号：US20250072059A1
公开(公告)日：2025-02-27
申请号：US18455500
申请日：2023-08-24
Applicant: QUALCOMM Incorporated
Inventor： Ravi Pramod Kumar VEDULA , Abhijeet PAUL , Hyunchul JUNG
IPC: H01L29/78 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/66
Abstract: A radio frequency (RF) device is described. The RF device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The RF device also includes a transistor including a source region and a drain region in the first-type diffusion region, a gate region between the source region and the drain region, and a body region. The RF device further includes a second-type diffusion region, comprising a gate overlap region partially overlapped by the gate region to define the body region and a second-type diffusion encroachment region in the source region and adjoining the gate overlap region to form a body terminal region, in which a silicidation layer shorts the body terminal region to the source region.
-
公开(公告)号：US20240063790A1
公开(公告)日：2024-02-22
申请号：US18104409
申请日：2023-02-01
Applicant: QUALCOMM Incorporated
Inventor： Ravi Pramod Kumar VEDULA , Abhijeet PAUL , Hyunchul JUNG
IPC: H03K17/687
CPC classification number: H03K17/6872 , H03K17/6874 , H03K2217/0036
Abstract: A radio frequency (RF) device is described. The RF device includes a switch field effect transistor (FET), having a source region, a drain region, a body region, and a gate region. The RF device also includes a dynamic bias control circuit. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor, and the gate region of the switch FET, by the gate resistor.
-
Patent Agency Ranking
公开(公告)号：US20240063787A1
公开(公告)日：2024-02-22
申请号：US17892800
申请日：2022-08-22
Applicant: QUALCOMM Incorporated
Inventor： Ravi Pramod Kumar VEDULA , Abhijeet PAUL , Hyunchul JUNG
IPC: H03K17/687
CPC classification number: H03K17/687 , H01L27/1203
Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET). The switch FET includes a source region, a drain region, a body region, and a gate region. The RFIC also includes a dynamic bias control circuit. The dynamic bias control circuit includes at least one transistor coupled between the body region and the gate region of the switch FET.
-
公开(公告)号：US20240322791A1
公开(公告)日：2024-09-26
申请号：US18189779
申请日：2023-03-24
Applicant: QUALCOMM Incorporated
Inventor： Abhijeet PAUL , Jonghae KIM , Mishel MATLOUBIAN
CPC classification number: H03H9/173 , H03H3/02 , H03H2003/021
Abstract: Disclosed are techniques for an integrated circuit (IC) that includes one or more transistors on a substrate and an interconnection structure on the one or more transistors. The interconnection structure includes a semiconductor structure embedded in the interconnection structure. In an aspect, the semiconductor structure includes a cavity structure, a piezoelectric layer over the cavity structure, an upper conductive structure on the piezoelectric layer, and a first contact structure on the upper conductive structure. In an aspect, the cavity structure includes a bottom that is a part of a first etch stop layer over a substrate, a top that is a part of a second etch stop layer over the first etch stop layer, one or more sidewalls connecting the bottom and the top of the cavity structure, and a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls.
-
公开(公告)号：US20240321370A1
公开(公告)日：2024-09-26
申请号：US18187993
申请日：2023-03-22
Applicant: QUALCOMM Incorporated
Inventor： Abhijeet PAUL , Mishel MATLOUBIAN
IPC: G11C17/16 , H01L23/525 , H10B20/25
CPC classification number: G11C17/165 , H01L23/5252 , H10B20/25
Abstract: Disclosed are secure anti-fuse one-time programmable (OTP) bit cells. In an aspect, an OTP bit cell includes a P− well comprising an N+ region and a P+ region, a first contact electrically coupled to the N+ region of the P− well, a second contact electrically coupled to the P+ region of the P− well, an insulating layer disposed over a portion of the N+ region, a portion of the P− well, and a portion of the P+ region, a gate structure disposed over the insulating layer, and a third contact electrically coupled to the gate structure. In an unprogrammed mode, the insulating layer creates a high resistance between the third contact and the second contact, and in a programmed mode, a rupture in the insulating layer creates a low resistance between the third contact and the second contact.
-
公开(公告)号：US20240321369A1
公开(公告)日：2024-09-26
申请号：US18186734
申请日：2023-03-20
Applicant: QUALCOMM Incorporated
Inventor： Abhijeet PAUL , Mishel MATLOUBIAN
IPC: G11C17/16 , G11C17/18 , H01L23/525 , H10B20/25
CPC classification number: G11C17/165 , G11C17/18 , H01L23/5256 , H10B20/25
Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a conductive element on an isolation structure, a dielectric film, a first contact structure, wherein at least a portion of the dielectric film is disposed between the conductive element and the first contact structure, and a second contact structure disposed on and electrically coupled with the conductive element. The dielectric film is configured as a resistive element with the first contact structure and the second contact structure being terminals of the resistive element after a dielectric breakdown has occurred within the portion of the dielectric film. Also, the dielectric film is configured as an insulator of a capacitive element with the first contact structure and the second contact structure being terminals of the capacitive element in a case that no dielectric breakdown has occurred within the portion of the dielectric film.
-
公开(公告)号：US20240319127A1
公开(公告)日：2024-09-26
申请号：US18189494
申请日：2023-03-24
Applicant: QUALCOMM Incorporated
Inventor： Abhijeet PAUL , Mishel MATLOUBIAN
IPC: G01N27/22
CPC classification number: G01N27/225 , G01N27/228
Abstract: In an aspect, a device includes: a first patterned metal layer; a first dielectric layer disposed over the first patterned metal layer; a second patterned metal layer disposed over the first dielectric layer, wherein the first patterned metal layer, the first dielectric layer, and the second patterned metal layer form a first capacitor; a second moisture-sensitive dielectric layer disposed over the second patterned metal layer; and a third patterned metal layer disposed over the second moisture-sensitive dielectric layer, wherein the third patterned metal layer, the second moisture-sensitive dielectric layer, and the second patterned metal layer form a second capacitor that is moisture-sensitive, and the first patterned metal layer is further configured as a heating element to assist in removing moisture from the second moisture-sensitive dielectric layer of the second capacitor in response to provision of an electrical power to the first patterned metal layer.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.015 seconds)
