公开(公告)号：US20210035971A1

公开(公告)日：2021-02-04

申请号：US16825030

申请日：2020-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HYUN PARK ,  HEONJONG SHIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.

公开(公告)号：US20230146060A1

公开(公告)日：2023-05-11

申请号：US17838384

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGIL PARK ,  KYUMAN HWANG ,  JAE HYUN PARK ,  DOYOUNG CHOI ,  DAEWON HA

IPC: H01L29/66 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/06 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/0688 ,  H01L21/8221 ,  H01L21/823842

Abstract: Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source/drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source/drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.

公开(公告)号：US20250072107A1

公开(公告)日：2025-02-27

申请号：US18944448

申请日：2024-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20230261064A1

公开(公告)日：2023-08-17

申请号：US17933797

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG IL PARK ,  JAE HYUN PARK

IPC: H01L29/417 ,  H01L29/775 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/41733 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66439 ,  H01L29/401 ,  H01L27/1203 ,  H01L21/84 ,  H01L2029/42388 ,  H01L29/0665

Abstract: There is provided a semiconductor device having reduced contact resistance and enhanced performance. The semiconductor device includes a substrate, a first active pattern spaced apart from the substrate and extending in a first direction, and including a first two-dimensional semiconductor material, a first gate electrode extending in a second direction intersecting the first direction on the substrate, and through which the first active pattern penetrates, and a first source/drain contact which includes a first contact insertion film and a first filling metal film sequentially stacked on a side surface of the first gate electrode, and is connected to the first active pattern, wherein the first contact insertion film at least partially surrounds a lower surface, a side surface and an upper surface of an end portion of the first active pattern, and the first active pattern and the first contact insertion film form an ohmic contact.

公开(公告)号：US20220238518A1

公开(公告)日：2022-07-28

申请号：US17659069

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HYUN PARK ,  HEONJONG SHIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.

公开(公告)号：US20230138121A1

公开(公告)日：2023-05-04

申请号：US17805261

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.