Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source/drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source/drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.