公开(公告)号：US20160141392A1

公开(公告)日：2016-05-19

申请号：US15003288

申请日：2016-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  SUNG-DAE SUK ,  JAEHOO PARK ,  DONGHO CHA ,  DAEWON HA

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

Abstract translation: 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。

公开(公告)号：US20240244847A1

公开(公告)日：2024-07-18

申请号：US18243726

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  JEON IL LEE ,  DAEWON HA

IPC: H10B51/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L23/5283 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: A semiconductor device may include first stacks and second stacks, which are alternately disposed on a substrate in a first direction parallel to a top surface of the substrate, and first pads and second pads connecting the first stacks to the second stacks. Each of the first and second stacks may include a gate electrode, channel patterns, which enclose a side surface of the gate electrode and are spaced apart from each other, and first and second conductive lines connected to a corresponding channel pattern. The first and second conductive lines of the second stack may be disposed to be adjacent to the first and second conductive lines, respectively, of the first stack. The first and second pads may be connected to the first and second conductive lines, respectively, of the first and second stacks.

公开(公告)号：US20240032269A1

公开(公告)日：2024-01-25

申请号：US18479323

申请日：2023-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINGYU KIM ,  MUNHYEON KIM ,  DAEWON HA

IPC: H10B10/00 ,  H01L29/10 ,  G11C11/412

CPC classification number: H10B10/12 ,  H01L29/1033 ,  G11C11/412

Abstract: A method of manufacturing a semiconductor device includes forming a first sacrificial and first active layer on a substrate; forming a first mask pattern on a portion of the substrate; etching the first sacrificial and first active layer partially using the first mask pattern to expose a portion of a top surface of the substrate; forming a semiconductor layer on the exposed top surface of the substrate; forming sacrificial layers and active layers on the first active and semiconductor layer, the active layers including an uppermost second active layer; forming a second mask pattern on a portion of the second active layer; forming a trench using the second mask pattern, the trench defining a first and second active pattern; and removing the sacrificial layers to form a first and second channel patterns on the first and second active patterns, respectively, wherein the first active pattern includes the semiconductor layer.

公开(公告)号：US20230138121A1

公开(公告)日：2023-05-04

申请号：US17805261

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20230146060A1

公开(公告)日：2023-05-11

申请号：US17838384

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGIL PARK ,  KYUMAN HWANG ,  JAE HYUN PARK ,  DOYOUNG CHOI ,  DAEWON HA

IPC: H01L29/66 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/06 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/0688 ,  H01L21/8221 ,  H01L21/823842

Abstract: Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source/drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source/drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.

公开(公告)号：US20190312145A1

公开(公告)日：2019-10-10

申请号：US16437056

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEWON HA ,  SEUNGSEOK HA ,  BYOUNG HAK HONG

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US20180040699A1

公开(公告)日：2018-02-08

申请号：US15463187

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEWON HA ,  SEUNGSEOK HA ,  BYOUNG HAK HONG

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.

公开(公告)号：US20220231172A1

公开(公告)日：2022-07-21

申请号：US17398494

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEWON HA ,  MINGYU KIM ,  DOYOUNG CHOI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes, on a substrate, a channel pattern including semiconductor patterns, which are spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a gate electrode on the channel pattern, the gate electrode disposed on an uppermost semiconductor pattern of the semiconductor patterns and extended into regions between the semiconductor patterns, and a pair of gate spacers disposed on the uppermost semiconductor pattern to cover opposite side surfaces of the gate electrode, respectively. Each semiconductor pattern includes germanium. Each semiconductor pattern includes a pair of first portions vertically overlapped with the pair of gate spacers and a second portion between the pair of first portions. A thickness, in the first direction, of a pair of first portions of the uppermost semiconductor pattern is larger than a thickness, in the first direction, of the second portion of the uppermost semiconductor pattern.

公开(公告)号：US20220122994A1

公开(公告)日：2022-04-21

申请号：US17363748

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINGYU KIM ,  MUNHYEON KIM ,  DAEWON HA

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/10

Abstract: A semiconductor device may include a pull-down transistor and a pull-up transistor disposed on a substrate. Each of the pull-down transistor and the pull-up transistor may include an active pattern disposed on the substrate; two source/drain patterns disposed on the active pattern; a channel pattern interposed between the two source/drain patterns, the channel pattern including semiconductor patterns that are disposed in a noncontiguous stack, such that a semiconductor pattern does not contact an adjacent semiconductor pattern; and a gate electrode crossing the channel pattern in a first direction. There may be more or less semiconductor patterns of the pull-down transistor as compared to semiconductor patterns of the pull-up transistor.

公开(公告)号：US20210242349A1

公开(公告)日：2021-08-05

申请号：US17240616

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.