公开(公告)号：US20240032269A1

公开(公告)日：2024-01-25

申请号：US18479323

申请日：2023-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINGYU KIM ,  MUNHYEON KIM ,  DAEWON HA

IPC: H10B10/00 ,  H01L29/10 ,  G11C11/412

CPC classification number: H10B10/12 ,  H01L29/1033 ,  G11C11/412

Abstract: A method of manufacturing a semiconductor device includes forming a first sacrificial and first active layer on a substrate; forming a first mask pattern on a portion of the substrate; etching the first sacrificial and first active layer partially using the first mask pattern to expose a portion of a top surface of the substrate; forming a semiconductor layer on the exposed top surface of the substrate; forming sacrificial layers and active layers on the first active and semiconductor layer, the active layers including an uppermost second active layer; forming a second mask pattern on a portion of the second active layer; forming a trench using the second mask pattern, the trench defining a first and second active pattern; and removing the sacrificial layers to form a first and second channel patterns on the first and second active patterns, respectively, wherein the first active pattern includes the semiconductor layer.

公开(公告)号：US20220320083A1

公开(公告)日：2022-10-06

申请号：US17844807

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MUNHYEON KIM ,  YOUNGCHAI JUNG ,  MINGYU KIM ,  SEON-BAE KIM ,  YEONHO PARK

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

公开(公告)号：US20220231172A1

公开(公告)日：2022-07-21

申请号：US17398494

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEWON HA ,  MINGYU KIM ,  DOYOUNG CHOI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes, on a substrate, a channel pattern including semiconductor patterns, which are spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a gate electrode on the channel pattern, the gate electrode disposed on an uppermost semiconductor pattern of the semiconductor patterns and extended into regions between the semiconductor patterns, and a pair of gate spacers disposed on the uppermost semiconductor pattern to cover opposite side surfaces of the gate electrode, respectively. Each semiconductor pattern includes germanium. Each semiconductor pattern includes a pair of first portions vertically overlapped with the pair of gate spacers and a second portion between the pair of first portions. A thickness, in the first direction, of a pair of first portions of the uppermost semiconductor pattern is larger than a thickness, in the first direction, of the second portion of the uppermost semiconductor pattern.

公开(公告)号：US20220122994A1

公开(公告)日：2022-04-21

申请号：US17363748

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINGYU KIM ,  MUNHYEON KIM ,  DAEWON HA

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/10

Abstract: A semiconductor device may include a pull-down transistor and a pull-up transistor disposed on a substrate. Each of the pull-down transistor and the pull-up transistor may include an active pattern disposed on the substrate; two source/drain patterns disposed on the active pattern; a channel pattern interposed between the two source/drain patterns, the channel pattern including semiconductor patterns that are disposed in a noncontiguous stack, such that a semiconductor pattern does not contact an adjacent semiconductor pattern; and a gate electrode crossing the channel pattern in a first direction. There may be more or less semiconductor patterns of the pull-down transistor as compared to semiconductor patterns of the pull-up transistor.