公开(公告)号：US20230197858A1

公开(公告)日：2023-06-22

申请号：US18110961

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78645 ,  H01L29/6675 ,  H01L29/7827 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/78696

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20170019250A1

公开(公告)日：2017-01-19

申请号：US15168536

申请日：2016-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-CHUL LEE ,  HYOJIN KIM ,  JAE-WOOK LEE ,  SOOYOUNG WOO ,  KYU-SAM LEE

IPC: H04L9/06 ,  H04L9/30

CPC classification number: G06F21/44 ,  H04L9/3226 ,  H04L9/3263 ,  H04W12/10 ,  H04W12/12 ,  H04W88/02

Abstract: A display driver integrated circuit includes a seed generation block configured to generate a seed, an encryption block configured to encrypt the seed and generate a first encryption text, and a comparison block configured to receive a second encryption text, in which the seed is encrypted, from an application processor, compare the first encryption text with the second encryption text, and output a control signal based on the comparison result.

Abstract translation: 显示驱动器集成电路包括被配置为生成种子的种子生成块，被配置为加密种子并生成第一加密文本的加密块以及被配置为接收种子被加密的第二加密文本的比较块， 从应用处理器，将第一加密文本与第二加密文本进行比较，并根据比较结果输出控制信号。

公开(公告)号：US20240347609A1

公开(公告)日：2024-10-17

申请号：US18500499

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHOON HWANG ,  HYOJIN KIM ,  BYUNGHO MOON ,  MYUNGIL KANG ,  WOOSEOK PARK ,  JAEHO JEON

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active pattern, first and second source/drain patterns overlapping with the active pattern, a separation insulating layer between the first and second source/drain patterns, and first and second gate electrodes spaced apart from each other with the separation insulating layer interposed therebetween. A level of a top surface of the separation insulating layer is higher than a level of a top surface of the first gate electrode and a level of a top surface of the second gate electrode.

公开(公告)号：US20220416086A1

公开(公告)日：2022-12-29

申请号：US17711914

申请日：2022-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOJIN KIM ,  SANGMOON LEE ,  JINBUM KIM ,  YONGJUN NAM

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.

公开(公告)号：US20210242349A1

公开(公告)日：2021-08-05

申请号：US17240616

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20200027992A1

公开(公告)日：2020-01-23

申请号：US16504960

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.