公开(公告)号：US20230138121A1

公开(公告)日：2023-05-04

申请号：US17805261

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20250072107A1

公开(公告)日：2025-02-27

申请号：US18944448

申请日：2024-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20230146060A1

公开(公告)日：2023-05-11

申请号：US17838384

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGIL PARK ,  KYUMAN HWANG ,  JAE HYUN PARK ,  DOYOUNG CHOI ,  DAEWON HA

IPC: H01L29/66 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/06 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/0688 ,  H01L21/8221 ,  H01L21/823842

Abstract: Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source/drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source/drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.