公开(公告)号：US12124347B2

公开(公告)日：2024-10-22

申请号：US18152797

申请日：2023-01-11

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Gautam Tikoo ,  Harshit Saxena

IPC: G06F11/27 ,  G06F12/14

CPC classification number: G06F11/27 ,  G06F12/14 ,  G06F2212/1052

Abstract: An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.

公开(公告)号：US20230027878A1

公开(公告)日：2023-01-26

申请号：US17813737

申请日：2022-07-20

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Hemant Nautiyal ,  Andres Barrilado Gonzalez

IPC: G06F11/07

Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

公开(公告)号：US11175340B1

公开(公告)日：2021-11-16

申请号：US17175950

申请日：2021-02-15

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Shreya Singh

IPC: G01R31/00 ,  G01R31/3177 ,  G01R31/317

Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a set of fake fault injection circuits and a critical intellectual property (IP) core that includes first and second control circuits. The first and second control circuits are each operable in a test mode and a functional mode. The first and second control circuits are operated in the functional mode in lockstep in an absence of a fake fault input. In a presence of the fake fault input, one of the first and second control circuits is switched from the functional mode to the test mode. One of the first and second control circuits operating the test mode generates a fake fault response for the fake fault input. The critical IP core is determined as one of error-free and erroneous based on a detection of the generated fake fault response as one of error-free and erroneous, respectively.

公开(公告)号：US20240160745A1

公开(公告)日：2024-05-16

申请号：US18152809

申请日：2023-01-11

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Gautam Tikoo

IPC: G06F21/57 ,  G01R31/28 ,  G06F11/27 ,  G06F21/62 ,  G06F21/72

CPC classification number: G06F21/577 ,  G01R31/2851 ,  G06F11/27 ,  G06F21/6218 ,  G06F21/72 ,  G06F2221/034

Abstract: An integrated circuit includes a secure asset, a security system, and an efficacy decoder. The security system is triggered to operate in one of its functional states. Further, the security system receives various test requests for an access to the secure asset, and determines, based on the triggered functional state thereof, one or more test requests authorized to access the secure asset. The efficacy decoder similarly receives the test requests and determines one or more allowable requests for the triggered functional state of the security system. Further, the efficacy decoder determines an efficacy value for the security system based on a comparison between the test requests authorized by the security system and the allowable requests associated with the triggered functional state. The efficacy value is indicative of a security level of the security system operating in the triggered functional state.

公开(公告)号：US20220334936A1

公开(公告)日：2022-10-20

申请号：US17301927

申请日：2021-04-19

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Krishan Bansal

IPC: G06F11/263 ,  G06F9/52

Abstract: A lockstep testing system includes a lockstep controller that generates various control signals. The lockstep testing system further includes various lockstep circuitries, with each lockstep circuitry including primary and redundant functional circuits that are operable in a lockstep mode, and a fault injection circuit that receives a control signal from the lockstep controller and injects a transient fault in the corresponding lockstep circuitry. The transient fault can be injected at one of input and output stages of the primary and redundant functional circuits. Each lockstep circuitry further includes a checker circuit that tests whether the corresponding lockstep circuitry is faulty (i.e., whether the injected fault is accurately detected), and generates and provides, to the lockstep controller, a fault indication signal indicating whether the corresponding lockstep circuitry is faulty.

公开(公告)号：US11797373B2

公开(公告)日：2023-10-24

申请号：US17643958

申请日：2021-12-13

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Ankur Behl

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0706 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/0781

Abstract: An integrated circuit includes a functional circuit, a detection circuit, a processing circuit, and a recovery circuit. The detection circuit detects a fault in the functional circuit and generates a fault indication indicative of the detected fault. The processing circuit receives the fault indication and identifies a functional domain identifier (ID) associated with the fault. Based on the fault indication, the processing circuit generates context tag data that is indicative of a type of the fault and an operational state of the functional circuit when the fault is detected therein. Further, the processing circuit assigns a priority level to the fault based on the context tag data and the functional domain ID. The recovery circuit performs, based on the functional domain ID, the context tag data, and the first priority level, a recovery operation to recover the functional circuit from the fault.

公开(公告)号：US11550684B2

公开(公告)日：2023-01-10

申请号：US17301927

申请日：2021-04-19

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Krishan Bansal

IPC: G06F11/07 ,  G06F11/30 ,  G06F11/263 ,  G06F9/52

Abstract: A lockstep testing system includes a lockstep controller that generates various control signals. The lockstep testing system further includes various lockstep circuitries, with each lockstep circuitry including primary and redundant functional circuits that are operable in a lockstep mode, and a fault injection circuit that receives a control signal from the lockstep controller and injects a transient fault in the corresponding lockstep circuitry. The transient fault can be injected at one of input and output stages of the primary and redundant functional circuits. Each lockstep circuitry further includes a checker circuit that tests whether the corresponding lockstep circuitry is faulty (i.e., whether the injected fault is accurately detected), and generates and provides, to the lockstep controller, a fault indication signal indicating whether the corresponding lockstep circuitry is faulty.

公开(公告)号：US12105583B2

公开(公告)日：2024-10-01

申请号：US17813737

申请日：2022-07-20

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Hemant Nautiyal ,  Andres Barrilado Gonzalez

IPC: G06F11/07 ,  G06F11/00

CPC classification number: G06F11/0793 ,  G06F11/008 ,  G06F11/0706 ,  G06F11/0724 ,  G06F11/0757

Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

公开(公告)号：US20240160545A1

公开(公告)日：2024-05-16

申请号：US18152797

申请日：2023-01-11

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Gautam Tikoo ,  Harshit Saxena

IPC: G06F11/27 ,  G06F12/14

CPC classification number: G06F11/27 ,  G06F12/14 ,  G06F2212/1052

Abstract: An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.

公开(公告)号：US20230185656A1

公开(公告)日：2023-06-15

申请号：US17643958

申请日：2021-12-13

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Ankur Behl

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0751 ,  G06F11/0781

Abstract: An integrated circuit includes a functional circuit, a detection circuit, a processing circuit, and a recovery circuit. The detection circuit detects a fault in the functional circuit and generates a fault indication indicative of the detected fault. The processing circuit receives the fault indication and identifies a functional domain identifier (ID) associated with the fault. Based on the fault indication, the processing circuit generates context tag data that is indicative of a type of the fault and an operational state of the functional circuit when the fault is detected therein. Further, the processing circuit assigns a priority level to the fault based on the context tag data and the functional domain ID. The recovery circuit performs, based on the functional domain ID, the context tag data, and the first priority level, a recovery operation to recover the functional circuit from the fault.