公开(公告)号：US12105583B2

公开(公告)日：2024-10-01

申请号：US17813737

申请日：2022-07-20

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Hemant Nautiyal ,  Andres Barrilado Gonzalez

IPC: G06F11/07 ,  G06F11/00

CPC classification number: G06F11/0793 ,  G06F11/008 ,  G06F11/0706 ,  G06F11/0724 ,  G06F11/0757

Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

公开(公告)号：US20230027878A1

公开(公告)日：2023-01-26

申请号：US17813737

申请日：2022-07-20

Applicant: NXP B.V.

Inventor： Neha Srivastava ,  Hemant Nautiyal ,  Andres Barrilado Gonzalez

IPC: G06F11/07

Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

公开(公告)号：US20200073786A1

公开(公告)日：2020-03-05

申请号：US16411052

申请日：2019-05-13

Applicant: NXP B.V

Inventor： Jan-Peter Schat ,  Xavier Hours ,  Andres Barrilado Gonzalez

IPC: G06F11/36 ,  G06F11/26 ,  G01R31/3181 ,  G01R31/3167

Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

公开(公告)号：US20230171293A1

公开(公告)日：2023-06-01

申请号：US18057212

申请日：2022-11-20

Applicant: NXP B.V.

Inventor： Franck Galtie ,  Rolf Dieter Schlagenhaft ,  Andres Barrilado Gonzalez

IPC: H04L9/40

CPC classification number: H04L63/205 ,  H04L63/1416 ,  H04L63/0218

Abstract: An architecture for monitoring, analyzing, and reacting to safety and cybersecurity events has been disclosed. In at least one embodiment, a method for processing safety and security events of a system includes requesting a reaction or escalating an effect from a first controller of the system to a second controller of the system based on a subset of available reactions for a current context of the system, constraint information, a predetermined effect-reaction policy, and the effect.

公开(公告)号：US20240077578A1

公开(公告)日：2024-03-07

申请号：US18461673

申请日：2023-09-06

Applicant: NXP B.V.

Inventor： Cristian Pavao Moreira ,  Thierry Mesnard ,  Andres Barrilado Gonzalez ,  Mohamed Boulkheir ,  Didier Salle

IPC: G01S7/03 ,  G01S7/282 ,  G01S13/02 ,  G01S13/536

CPC classification number: G01S7/032 ,  G01S7/282 ,  G01S13/0209 ,  G01S13/536

Abstract: A system and method for a radar system are provided. The radar system includes a leader radar device that includes a first clock generation circuit configured to generate a first clock signal, and a first transmitter and receiver configured to transmit and receive radar signals using a first local oscillator signal. The system includes a follower radar device. The follower radar device is configured to receive the first clock signal and the first local oscillator signal from the leader radar device. The follower radar device includes a second clock generation circuit configured to generate a second clock signal, wherein, in a default operational mode of the radar system at least a portion of the second clock generation circuit is disabled, and a second transmitter and receiver configured to transmit and receive first radar signals.

公开(公告)号：US20240020786A1

公开(公告)日：2024-01-18

申请号：US18351968

申请日：2023-07-13

Applicant: NXP B.V.

Inventor： Andres Barrilado Gonzalez ,  Franck Galtie ,  Rolf Dieter Schlagenhaft ,  Hemant Nautiyal

IPC: G06Q50/26

CPC classification number: G06Q50/265

Abstract: An event manager for filtering safety and security events of a system including an event sequence list including predetermined event sequences in which each sequence includes at least one event identifier identifying a corresponding one of multiple monitored events, an event sequence array that stores a received event sequence in response to received event notifications, and a controller that stores an event identifier into the event sequence array and that determines whether the received event sequence matches at least one of the predetermined event sequences for determining a composite event and a response for each received event notification. The matching determination may be made with or without consideration of chronological order. A suspected composite event may be identified when multiple possible matches may exist, and a final composite event is ratified when only one match is found. An exception may be generated upon timeout of a timer.

公开(公告)号：US20240020186A1

公开(公告)日：2024-01-18

申请号：US18348403

申请日：2023-07-07

Applicant: NXP B.V.

Inventor： Xiankun Jin ,  Andres Barrilado Gonzalez ,  Mathieu Blazy-Winning

IPC: G06F11/00 ,  G06F11/32

CPC classification number: G06F11/008 ,  G06F11/324

Abstract: A layered architecture for managing health of the electronic system comprises a plurality of health subsystems. Health subsystems receive health information from health monitors coupled to respective components of the electronic system and provide the health information to another health subsystem. Based on the received health information, the other health subsystem uses predictive data analytics to determine a health condition of the electronic system and update a health policy based on the predictive data analytics to improve prediction of the health condition of the electronic system.