公开(公告)号：US20190004958A1

公开(公告)日：2019-01-03

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US11327894B2

公开(公告)日：2022-05-10

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US11816036B2

公开(公告)日：2023-11-14

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

CPC classification number: G06F12/0868 ,  G06F3/065 ,  G06F3/068 ,  G06F3/0619 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/311 ,  G06F2212/6046

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20220261351A1

公开(公告)日：2022-08-18

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20210049102A1

公开(公告)日：2021-02-18

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US10606755B2

公开(公告)日：2020-03-31

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.