公开(公告)号：US11385704B2

公开(公告)日：2022-07-12

申请号：US17183518

申请日：2021-02-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US20210200685A1

公开(公告)日：2021-07-01

申请号：US16729371

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomar Stark

IPC: G06F12/0895 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/1045

Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

公开(公告)号：US10891230B1

公开(公告)日：2021-01-12

申请号：US16458017

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Igor Yanover

IPC: G06F9/34 ,  G06F12/0811

Abstract: Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

公开(公告)号：US20200310511A1

公开(公告)日：2020-10-01

申请号：US16369793

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC: G06F1/324 ,  G06F1/3206

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US10095522B2

公开(公告)日：2018-10-09

申请号：US14581268

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/30

Abstract: A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

公开(公告)号：US09710389B2

公开(公告)日：2017-07-18

申请号：US14643354

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Oleg Margulis ,  Sumit Ahuja ,  Polychronis Xekalakis ,  Yongjun Park ,  Vineeth Mekkat ,  Igor Yanover ,  Sebastian Winkel ,  Ethan Schuchman

IPC: G06F12/06 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F12/0875 ,  G06F9/38 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/467 ,  G06F2212/1008 ,  G06F2212/452

Abstract: A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.

公开(公告)号：US09292362B2

公开(公告)日：2016-03-22

申请号：US13926089

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Lev Makovsky ,  Zeev Sperber ,  Efraim Rotem ,  Nir Rosenzweig ,  Stanislav Shwartsman ,  Raanan Sade ,  Igor Yanover ,  Gavri Berger ,  Tomer Weiner ,  Ron Gabor

IPC: G06F1/04 ,  G06F9/54 ,  G06F9/30 ,  G06F9/48 ,  G06F1/32

CPC classification number: G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US11681533B2

公开(公告)日：2023-06-20

申请号：US16443593

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Alaa Alameldeen ,  Abhishek Basak ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Carlos Rozas ,  Igor Yanover ,  Xiang Zou

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027 ,  G06F21/57

CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/30189 ,  G06F12/1027 ,  G06F21/57 ,  G06F2212/68 ,  G06F2221/034

Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

公开(公告)号：US20200272474A1

公开(公告)日：2020-08-27

申请号：US16443593

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Alaa Alameldeen ,  Abhishek Basak ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Carlos Rozas ,  Igor Yanover ,  Xiang Zou

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/1027 ,  G06F21/57

Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

公开(公告)号：US10324857B2

公开(公告)日：2019-06-18

申请号：US15416549

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Joseph Nuzman ,  Raanan Sade ,  Igor Yanover ,  Ron Gabor ,  Amit Gradstein

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1027

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.