公开(公告)号：US20220207147A1

公开(公告)日：2022-06-30

申请号：US17134343

申请日：2020-12-26

申请人： Intel Corporation

发明人： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F21/57 ,  G06F21/54 ,  G06F9/30

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.

公开(公告)号：US10922088B2

公开(公告)日：2021-02-16

申请号：US16024733

申请日：2018-06-29

申请人： Intel Corporation

发明人： Fangfei Liu ,  Bin Xing ,  Michael Steiner ,  Mona Vij ,  Carlos Rozas ,  Francis McKeen ,  Meltem Ozsoy ,  Matthew Fernandez ,  Krystof Zmudzinski ,  Mark Shanahan

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F21/55

摘要： Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.

公开(公告)号：US11681533B2

公开(公告)日：2023-06-20

申请号：US16443593

申请日：2019-06-17

申请人： Intel Corporation

发明人： Ron Gabor ,  Alaa Alameldeen ,  Abhishek Basak ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Carlos Rozas ,  Igor Yanover ,  Xiang Zou

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/1027 ,  G06F21/57

CPC分类号： G06F9/3842 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/30189 ,  G06F12/1027 ,  G06F21/57 ,  G06F2212/68 ,  G06F2221/034

摘要： Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

公开(公告)号：US20220206818A1

公开(公告)日：2022-06-30

申请号：US17134334

申请日：2020-12-26

申请人： Intel Corporation

发明人： Alaa Alameldeen ,  Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F21/57

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.

公开(公告)号：US20220083347A1

公开(公告)日：2022-03-17

申请号：US17019880

申请日：2020-09-14

申请人： Intel Corporation

发明人： Scott Constable ,  Bin Xing ,  Fangfei Liu ,  Thomas Unterluggauer ,  Krystof Zmudzinski

IPC分类号： G06F9/4401 ,  G06F9/30

摘要： A method comprises receiving an instruction to resume operations of an enclave in a cloud computing environment and generating a pseud-random time delay before resuming operations of the enclave in the cloud computing environment.

公开(公告)号：US20200272474A1

公开(公告)日：2020-08-27

申请号：US16443593

申请日：2019-06-17

申请人： Intel Corporation

发明人： Ron Gabor ,  Alaa Alameldeen ,  Abhishek Basak ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Carlos Rozas ,  Igor Yanover ,  Xiang Zou

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/1027 ,  G06F21/57

摘要： Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

公开(公告)号：US20230350814A1

公开(公告)日：2023-11-02

申请号：US18078762

申请日：2022-12-09

申请人： Intel Corporation

发明人： Thomas Unterluggauer ,  Fangfei Liu ,  Carlos Rozas ,  Scott Constable ,  Gilles Pokam ,  Francis McKeen ,  Christopher Wilkerson ,  Erik Hallnor

IPC分类号： G06F12/14 ,  G06F12/0815 ,  G06F12/121

CPC分类号： G06F12/1408 ,  G06F12/0815 ,  G06F12/121 ,  G06F2212/1052

摘要： Techniques and mechanisms for a victim cache to operate in conjunction with another cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a primary cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the primary cache. The victim cache is accessed using an independently randomized mapping. Subsequently, a request to access the first line results in a search of the victim cache and the primary cache. Based on the search, the first line is evicted from the victim cache, and reinserted in the primary cache. In another embodiment, reinsertion of the first line in the primary cache includes the first line and a third line being swapped between the primary cache and the victim cache.

公开(公告)号：US20220207138A1

公开(公告)日：2022-06-30

申请号：US17134350

申请日：2020-12-26

申请人： Intel Corporation

发明人： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F21/55 ,  G06F21/54 ,  G06F9/30 ,  G06F9/38

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.

公开(公告)号：US20220200783A1

公开(公告)日：2022-06-23

申请号：US17127786

申请日：2020-12-18

申请人： Intel Corporation

发明人： Thomas Unterluggauer ,  Alaa Alameldeen ,  Scott Constable ,  Fangfei Liu ,  Francis McKeen ,  Carlos Rozas ,  Anna Trikalinou

IPC分类号： H04L9/00 ,  G06F21/72

摘要： Techniques and mechanisms for a victim cache to operate in conjunction with a skewed cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a skewed cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the skewed cache. Subsequently, a request to access the first line results in a search of both the victim cache and sets of the skewed cache which have been mapped to an address corresponding to the first line. Based on the search, the first line is evicted from the victim cache, and reinserted in the skewed cache. In another embodiment, reinsertion of the first line in the skewed cache includes the first line and a third line being swapped between the skewed cache and the victim cache.

公开(公告)号：US12001346B2

公开(公告)日：2024-06-04

申请号：US17127786

申请日：2020-12-18

申请人： Intel Corporation

发明人： Thomas Unterluggauer ,  Alaa Alameldeen ,  Scott Constable ,  Fangfei Liu ,  Francis McKeen ,  Carlos Rozas ,  Anna Trikalinou

IPC分类号： G06F12/10 ,  G06F12/121 ,  G06F12/14

CPC分类号： G06F12/14 ,  G06F12/121 ,  G06F2212/1052

摘要： Techniques and mechanisms for a victim cache to operate in conjunction with a skewed cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a skewed cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the skewed cache. Subsequently, a request to access the first line results in a search of both the victim cache and sets of the skewed cache which have been mapped to an address corresponding to the first line. Based on the search, the first line is evicted from the victim cache, and reinserted in the skewed cache. In another embodiment, reinsertion of the first line in the skewed cache includes the first line and a third line being swapped between the skewed cache and the victim cache.