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    CRYPTOGRAPHIC COMPUTING WITH DISAGGREGATED MEMORY
    2.
    发明申请
    CRYPTOGRAPHIC COMPUTING WITH DISAGGREGATED MEMORY 有权

    公开(公告)号：US20210117340A1

    公开(公告)日：2021-04-22

    申请号：US17134332

    申请日：2020-12-26

    Applicant: Intel Corporation

    Inventor： Anna Trikalinou ,  Abhishek Basak

    IPC: G06F12/14 ,  G06F12/06 ,  G06F9/50

    Abstract: In one embodiment, an application executing on a host node allocates a memory address of a remote node. The application selects, based at least in part on device capability information for the host and remote nodes, one of the host node or the remote node to encrypt application data, and configures the selected node to encrypt the application data based on a key and a pointer to the memory address of the remote node.

    SECURITY AWARE PREFETCH MECHANISM
    3.
    发明申请
    SECURITY AWARE PREFETCH MECHANISM 有权

    公开(公告)号：US20210110031A1

    公开(公告)日：2021-04-15

    申请号：US17132010

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Abhishek Basak ,  Erdem Aktas

    IPC: G06F21/54 ,  G06F21/55 ,  G06F21/79 ,  G06F12/0882 ,  G06F12/0862 ,  G06F12/14

    Abstract: An apparatus to facilitate data cache security is disclosed. The apparatus includes a cache memory to store data; and prefetch hardware to pre-fetch data to be stored in the cache memory, including a cache set monitor hardware to determine critical cache addresses to monitor to determine processes that retrieve data from the cache memory; and pattern monitor hardware to monitor cache access patterns to the critical cache addresses to detect potential side-channel cache attacks on the cache memory by an attacker process.

    Techniques for control flow protection
    6.
    发明授权
    Techniques for control flow protection 有权

    公开(公告)号：US10360374B2

    公开(公告)日：2019-07-23

    申请号：US15605573

    申请日：2017-05-25

    Applicant: INTEL CORPORATION

    Inventor： Abhishek Basak ,  Ravi L. Sahita ,  Vedvyas Shanbhogue

    IPC: G06F21/00 ,  G06F21/52 ,  G06F12/06

    Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.

    Techniques to compress cryptographic metadata for memory encryption
    7.
    发明授权
    Techniques to compress cryptographic metadata for memory encryption 有权

    公开(公告)号：US10025956B2

    公开(公告)日：2018-07-17

    申请号：US14975588

    申请日：2015-12-18

    Applicant: Intel Corporation

    Inventor： Abhishek Basak ,  Siddhartha Chhabra ,  Jungju Oh ,  David M. Durham

    IPC: G06F21/79 ,  G06F3/06 ,  G06F12/0891 ,  G06F12/123 ,  G06F12/14 ,  H04L9/06

    Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.

    CRYPTOGRAPHIC COMPUTING IN MULTITENANT ENVIRONMENTS
    9.
    发明申请
    CRYPTOGRAPHIC COMPUTING IN MULTITENANT ENVIRONMENTS 有权

    公开(公告)号：US20230027329A1

    公开(公告)日：2023-01-26

    申请号：US17791000

    申请日：2020-12-26

    Applicant: Intel Corporation

    Inventor： David M. Durham ,  Michael D. LeMay ,  Salmin Sultana ,  Karanvir S. Grewal ,  Michael E. Kounavis ,  Sergej Deutsch ,  Andrew James Weiler ,  Abhishek Basak ,  Dan Baum ,  Santosh Ghosh

    IPC: G06F21/60 ,  G06F21/79 ,  G06F21/54

    Abstract: A processor, a system, a machine readable medium, and a method. The processor comprises first circuitry to: encrypt a first code image using a first code key; load the encrypted first code image into a memory area allocated in memory for the first code image by an operating system miming on the processor; and send to the operating system a substitute key that corresponds to the first code key, wherein the first code key is concealed from the operating system; and an instruction cache including control circuitry; and second circuitry coupled to the instruction cache, the second circuitry to: receive the substitute key from the operating system; in response to a first request from the operating system to execute the first code image to instantiate a first process, perform a first cryptographic function using a hardware key to generate the first code key from the substitute key; and program the control circuitry of the instruction cache with the first code key to enable the first code image to be decrypted using the first code key.

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