Invention Grant
- Patent Title: Technologies for controlling memory access transactions received from one or more I/O devices
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Application No.: US17109742Application Date: 2020-12-02
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Publication No.: US11625275B2Publication Date: 2023-04-11
- Inventor: Krystof Zmudzinski , Siddhartha Chhabra , Reshma Lal , Alpa Narendra Trivedi , Luis S. Kida , Pradeep M. Pappachan , Abhishek Basak , Anna Trikalinou
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F9/445
- IPC: G06F9/445 ; G06F9/50 ; G06F9/455 ; G06F21/62 ; G06F12/1009 ; G06F9/46 ; G06F13/28 ; G06F21/85 ; G06F21/78 ; G06F21/53 ; G06F21/57 ; H04L9/32 ; H04W12/30 ; H04W12/48 ; H04L69/16

Abstract:
Technologies for secure I/O include a compute device, which further includes a processor, a memory, a trusted execution environment (TEE), one or more input/output (I/O) devices, and an I/O subsystem. The I/O subsystem includes a device memory access table (DMAT) programmed by the TEE to establish bindings between the TEE and one or more I/O devices that the TEE trusts and a memory ownership table (MOT) programmed by the TEE when a memory page is allocated to the TEE.
Public/Granted literature
- US20210117576A1 TECHNOLOGIES FOR CONTROLLING MEMORY ACCESS TRANSACTIONS RECEIVED FROM ONE OR MORE I/O DEVICES Public/Granted day:2021-04-22
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